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參數(shù)資料
| 型號： | ORT8850H-1BM680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 30/105頁 |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
30
performed, one extra payload byte is inserted into the SONET frame. The H3 byte is used to hold this extra byte
and is hence called the pointer action byte. When justication is not being performed, this byte contains a default
value of 0x00.
B2 - Line Bit-Interleaved Parity code (BIP-8) byte - This byte carries the parity information which is used to check
for transmission errors in a line. This is a even parity computed over all the bytes of the frame, except section
overhead bytes, before scrambling. The computed parity value is transmitted in the next frame in the B2 position.
This byte is dened for all the STS-1signals in an STS-N signal.
K1, K2 - Automatic Protection Switching (APS channel) bytes - These bytes carry the APS information. They are
used for implementing automatic protection switching and for transmitting the line Alarm Indication Signal (AIS-L)
and the Remote Defect Indication (RDI-L) signal.
D4 to D12 - Line Data Communications Channel (DCC) bytes - These bytes provide a 576 Kbits/s channel for
transmission of information.
S1- Synchronization Status - This byte carries the synchronization status of the network element. It is located in
the rst STS-1 of an STS-N. Bits 5 through 8 (as dened in GR-253) of this byte carry the synchronization status.
Z1 - Growth - This byte is located in the second through Nth STS-1s of an STS-N and are allocated for future
growth. An STS-1 signal does not contain a Z1 byte.
M0 - STS-1 REI-L - This byte is dened only for STS-1 signals and is used to convey the Line Remote Error Indi-
cation (REI-L). The REI-L is the count of the number of B2 parity errors detected by an LTE and is transmitted to
its peer LTE as feedback information. Bits 5 through 8 of this byte are used for this function.
E2 - Orderwire byte - This byte carries for line orderwire information.
In the ORT8850 transmit path, the TOH processing is conned to the framing and byte interleaved parity bytes. The
remaining bytes are either passed through transparently or inserted from data sent from the serial TOH interface.
In the receive direction, the TOH bytes are stripped and optionally sent to the FPGA logic through the serial TOH
interface. Regenerated framing bytes are sent to the FPGA on the parallel data bus. The APS bytes K1 and K2 can
be optionally passed through the pointer mover under software control, or can be set to zero. The header bytes, J0
and C1 are also detected and used by the receive path, as will be discussed in a later section.
The serial TOH processing block is clocked by the TOH_CLK. If using the TOH bytes in the serial insertion mode to
support a communication channel, this TOH_CLK should be driven from the FPGA interface. The TOH processor
operates from 25 MHz to 106 MHz. A domain clock transfer takes place inside the TOH block and the TOH proces-
sor does not need to run as fast as the data.
Transparent Insert Mode
In the transmit direction the SPE and TOH data received on parallel input bus is transferred unaltered to the serial
LVDS output. However, B1 byte of STS-1 is always replaced with a new calculated value (the 11 bytes following B1
are replaced with all zeros). Also, A1 and A2 bytes of all STS-1s are always regenerated. The source for the TOH
bytes in the transparent mode is summarized in Table 9. (The order of transmission is row by row, left to right, and
then from top to bottom [most signicant bit rst]. SPE bytes are not shown.)
Table 9. Transmitter TOH on LVDS Output (Transparent Mode)
A1
A2
B1
0
Regenerated bytes.
Transparent bytes from parallel input port.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT8850H-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-2BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-2BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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