參數(shù)資料
型號(hào): ORT82G5-1BM680
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝: PLASTIC, BGA-680
文件頁(yè)數(shù): 68/110頁(yè)
文件大?。?/td> 1459K
代理商: ORT82G5-1BM680
60
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Clocking Recommendations for ORT82G5 (continued)
Option 2: Synchronous Reference Clocks to Rx and Tx Devices
In this type of clocking, a single reference clock is distributed to all receive and transmit devices in a system (Figure
20). This distributed clocking scheme will permit maximum exibility in the usage of transmit and receive channels
in the current silicon such as:
All transmit and receive channels can be used within any quad in receive channel alignment or alignment bypass
mode.
In channel alignment mode, each receive channel operates on its own independent clock domain.
The disadvantage with this scheme is the fact that it is difcult to distribute a 156 MHz reference clock across a
backplane. This may require expensive clock driver chips on the board to drive clocks to different destinations
within the specied jitter limits for the reference clock.
2730(F)
Figure 20. Distributed Reference Clock to Rx And Tx Devices
REFCLK
PORT CARD #1
ORT82G5
PORT CARD #2
TX1
TX2
BACKPLANE
AA
AB
ORT82G5
SWITCH
ORT82G5
CARD
相關(guān)PDF資料
PDF描述
ORT82G5-2BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORT82G5-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
OS10040280G-012 FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR
OT-WBSC-Y-A-10-X-9-M-3-05-FA FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR
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