參數(shù)資料
型號： ORT82G5-1BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 59/110頁
文件大?。?/td> 1459K
代理商： ORT82G5-1BM680
52
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES B Transmit Channel Conguration Registers
30102
—
TXHR_BA
Transmit Half Rate
Selection Bit, Bank
B, Channel A.
When TXHR = 1,
the transmitter sam-
ples data on the fall-
ing edge of the TBC
clock. When TXHR
= 0, the transmitter
samples data on the
falling edge of the
double rate clock
(derived from TBC).
TXHR = 0 on device
reset.
PWRDNT_BA
Transmit Power-
down Control
Bit, Bank B,
Channel A.
When PWRDNT
= 1, sections of
the transmit
hardware are
powered down
to conserve
power.
PWRDNT = 0
on device reset.
PE0_BA
Transmit Pre-
emphasis Selec-
tion Bit 0, Bank
B, Channel A.
PE0, together
with PE1,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE0 = 0 on
device reset.
PE1_BA
Transmit Pre-
emphasis Selec-
tion Bit 1, Bank
B, Channel A.
PE1, together
with PE0,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE1 = 0 on
device reset.
HAMP_BA
Transmit Half
Amplitude Selec-
tion Bit, Bank B,
Channel A. When
HAMP = 1, the
transmit output
buffer voltage
swing is limited to
half its amplitude.
Otherwise, the
transmit output
buffer maintains
its full voltage
swing. HAMP = 0
on device reset.
TBCKSEL_BA
Transmit Byte
Clock Selection
Bit, Bank B,
Channel A.
When TBCK-
SEL = 0, the
internal XCK is
selected. Other-
wise, the TBC
clock is
selected. TBCK-
SEL = 0 on
device reset.
RSVD
8B10BT_BA
Transmit 8B/
10B Encoder
Enable Bit, Bank
B, Channel A.
When 8B10BT =
1, the 8B/10B
encoder on the
transmit path is
enabled. Other-
wise, it is
bypassed.
8B10BT = 0 on
device reset.
00
30112
—
TXHR_BB
Transmit Half Rate
Selection Bit, Bank
B, Channel B.
When TXHR = 1,
the transmitter sam-
ples data on the fall-
ing edge of the TBC
clock. When TXHR
= 0, the transmitter
samples data on the
falling edge of the
double rate clock
(derived from TBC).
TXHR = 0 on device
reset.
PWRDNT_BB
Transmit Power-
down Control
Bit, Bank B,
Channel B.
When PWRDNT
= 1, sections of
the transmit
hardware are
powered down
to conserve
power.
PWRDNT = 0
on device reset.
PE0_BB
Transmit Pre-
emphasis Selec-
tion Bit 0, Bank
B, Channel B.
PE0, together
with PE1,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE0 = 0 on
device reset.
PE1_BB
Transmit Pre-
emphasis Selec-
tion Bit 1, Bank
B, Channel B.
PE1, together
with PE0,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE1 = 0 on
device reset.
HAMP_BB
Transmit Half
Amplitude Selec-
tion Bit, Bank B,
Channel B. When
HAMP = 1, the
transmit output
buffer voltage
swing is limited to
half its amplitude.
Otherwise, the
transmit output
buffer maintains
its full voltage
swing. HAMP = 0
on device reset.
TBCKSEL_BB
Transmit Byte
Clock Selection
Bit, Bank B,
Channel B.
When TBCK-
SEL = 0, the
internal XCK is
selected. Other-
wise, the TBC
clock is
selected. TBCK-
SEL = 0 on
device reset.
RSVD
8B10BT_BB
Transmit 8B/
10B Encoder
Enable Bit, Bank
B, Channel B.
When 8B10BT =
1, the 8B/10B
encoder on the
transmit path is
enabled. Other-
wise, it is
bypassed.
8B10BT = 0 on
device reset.
00
30122
—
TXHR_BC
Transmit Half Rate
Selection Bit, Bank
B, Channel C.
When TXHR = 1,
the transmitter sam-
ples data on the fall-
ing edge of the TBC
clock. When TXHR
= 0, the transmitter
samples data on the
falling edge of the
double rate clock
(derived from TBC).
TXHR = 0 on device
reset.
PWRDNT_BC
Transmit Power-
down Control
Bit, Bank B,
Channel C.
When PWRDNT
= 1, sections of
the transmit
hardware are
powered down
to conserve
power.
PWRDNT = 0
on device reset.
PE0_BC
Transmit Pre-
emphasis Selec-
tion Bit 0, Bank
B, Channel C.
PE0, together
with PE1,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE0 = 0 on
device reset.
PE1_BC
Transmit Pre-
emphasis Selec-
tion Bit 1, Bank
B, Channel C.
PE1, together
with PE0,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE1 = 0 on
device reset.
HAMP_BC
Transmit Half
Amplitude Selec-
tion Bit, Bank B,
Channel C. When
HAMP = 1, the
transmit output
buffer voltage
swing is limited to
half its amplitude.
Otherwise, the
transmit output
buffer maintains
its full voltage
swing. HAMP = 0
on device reset.
TBCKSEL_BC
Transmit Byte
Clock Selection
Bit, Bank B,
Channel C.
When TBCK-
SEL = 0, the
internal XCK is
selected. Other-
wise, the TBC
clock is
selected. TBCK-
SEL = 0 on
device reset.
RSVD
8B10BT_BC
Transmit 8B/
10B Encoder
Enable Bit, Bank
B, Channel C.
When 8B10BT =
1, the 8B/10B
encoder on the
transmit path is
enabled. Other-
wise, it is
bypassed.
8B10BT = 0 on
device reset.
00
30132
—
TXHR_BD
Transmit Half Rate
Selection Bit, Bank
B, Channel D.
When TXHR = 1,
the transmitter sam-
ples data on the fall-
ing edge of the TBC
clock. When TXHR
= 0, the transmitter
samples data on the
falling edge of the
double rate clock
(derived from TBC).
TXHR = 0 on device
reset.
PWRDNT_BD
Transmit Power-
down Control
Bit, Bank B,
Channel D.
When PWRDNT
= 1, sections of
the transmit
hardware are
powered down
to conserve
power.
PWRDNT = 0
on device reset.
PE0_BD
Transmit Pre-
emphasis Selec-
tion Bit 0, Bank
B, Channel D.
PE0, together
with PE1,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE0 = 0 on
device reset.
PE1_BD
Transmit Pre-
emphasis Selec-
tion Bit 1, Bank
B, Channel D.
PE1, together
with PE0,
selects one of
three preempha-
sis settings for
the transmit sec-
tion. PE1 = 0 on
device reset.
HAMP_BD
Transmit Half
Amplitude Selec-
tion Bit, Bank B,
Channel D. When
HAMP = 1, the
transmit output
buffer voltage
swing is limited to
half its amplitude.
Otherwise, the
transmit output
buffer maintains
its full voltage
swing. HAMP = 0
on device reset.
TBCKSEL_BD
Transmit Byte
Clock Selection
Bit, Bank B,
Channel D.
When TBCK-
SEL = 0, the
internal XCK is
selected. Other-
wise, the TBC
clock is
selected. TBCK-
SEL = 0 on
device reset.
RSVD
8B10BT_BD
Transmit 8B/
10B Encoder
Enable Bit, Bank
B, Channel D.
When 8B10BT =
1, the 8B/10B
encoder on the
transmit path is
enabled. Other-
wise, it is
bypassed.
8B10BT = 0 on
device reset.
00
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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