參數(shù)資料
型號(hào)： ORT82G5-1BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁(yè)數(shù)： 45/110頁(yè)
文件大?。?/td> 1459K
代理商： ORT82G5-1BM680
4
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Embedded Function Features
■
High-speed SERDES with programmable serial data
rates including 1.0 Gbits/s, 1.25 Gbits/s, 2.5 Gbits/s,
3.125 Gbits/s, and 3.5 Gbits/s. Operation has been
demonstrated on design tolerance devices at
4.25 Gbits/s across 20 in. of FR-4 backplane and at
3.2 Gbits/s across 40 in. of FR-4 backplane.
■
Asynchronous operation per receive channel with the
receiver frequency tolerance based on one reference
clock per quad channels (separate PLL per channel).
■
Ability to select full-rate or half-rate operation per Tx
or Rx channel by setting the appropriate control reg-
isters.
■
Programmable one-half amplitude transmit mode for
reduced power in chip-to-chip application.
■
Transmit preemphasis (programmable) for improved
receive data eye opening.
■
Receiver energy detector to determine if a link is
active. Optional automatic power-down for inactive
channels.
■
32-bit (8b/10b) or 40-bit (raw data) parallel internal
bus for data processing in FPGA logic.
■
Provides a 10 Gbits/s backplane interface to switch
fabric with protection. Also supports port cards at
40 Gbits/s or 2.5 Gbits/s.
■
3.125 Gbits/s SERDES compliant with XAUI serial
data specication for 10 Gbit Ethernet applications
with protection.
■
Most XAUI features for 10 Gbit Ethernet are embed-
ded including the required link state machine.
■
Compliant to bre-channel physical layer specica-
tion.
■
High-speed interface (HSI) function for clock/data
recovery serial backplane data transfer without exter-
nal clocks.
■
Eight-channel HSI function provides 2.5 Gbits/s
serial user data interface per channel for a total chip
bandwidth of 20 Gbits/s (full duplex).
■
SERDES has low-power CML buffers. Support for
1.5 V/1.8 V I/Os. Allows use with optical transceiver,
coaxial copper media, shielded twisted pair wiring or
high-speed backplanes such as FR-4.
■
Powerdown option of SERDES HSI receiver or trans-
mitter on a per-channel basis.
■
Automatic lock to reference clock in the absence of
valid receive data.
■
Per channel PRBS generator and checker.
■
High-speed (serial) and low-speed (parallel) loop-
back test modes.
■
Requires no external component for clock recovery
and frequency synthesis.
■
SERDES characterization pins available to control/
monitor the internal interface to one SERDES quad
macro.
■
SERDES HSI automatically recovers from loss-of-
clock once its reference clock returns to normal oper-
ating state.
■
Built-in boundary scan (IEEE 1149.1 and 1149.2
JTAG) for the programmable I/Os, not including the
SERDES interface.
■
FIFOs align incoming data across all eight channels
(all eight channels, two groups of four channels, or
four groups of two channels). Alignment is done
using comma characters or /A/ character in XAUI
mode. Optional ability to bypass alignment FIFOs for
asynchronous operation between channels. (Each
channel includes its own clock and frame pulse or
comma detect.)
■
Addition of two 4K X 36 dual-port RAMs with access
to the programmable logic.
■
Pinout compatible to the ORCA ORSO82G5 SONET
backplane driver FPSC in the 680 PBGAM package.
Intellectual Property Features
Programmable logic provides a variety of yet-to-be
standardized interface functions, including the following
Lattice IP core functions:
■
10 Gbits/s Ethernet as dened by IEEE 802.3ae:
— XGMII for interfacing to 10 Gbits/s Ethernet MACs
(media access controller). XGMII is a 156 MHz
double data rate parallel short reach (typically
less than 2") interconnect interface.
— XAUI to XGMII translator (XGXS), including sup-
port for dual XAUI ports for 1 + 1 XAUI protection.
■
POS-PHY4 interface for 10 Gbits/s SONET/SDH and
OTN systems and some 10 Gbits/s Ethernet systems
to allow easy integration of InniBand, bre-channel,
and 10 Gbits/s Ethernet in data over bre applica-
tions.
■
Ethernet MAC functions at 10/100 Mbits/s, 1 Gbits/s,
and 10 Gbits/s.
■
Backplane drivers for industry standard products,
including 2.5 Gbits/s and 10Gbps Network Proces-
sors and 2.5Gbps and 10Gbps Switch fabrics such
as the Pi-family (Pi-X, Pi-C).
■
Other functions such as bre-channel (including bre
channel XAUI) and InniBand link layer IP cores are
also planned.
■
XAUI interface to emerging RPR (resilient packet
ring) MAC solution.
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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