參數(shù)資料
型號： ORT82G5-1BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 50/110頁
文件大?。?/td> 1459K
代理商： ORT82G5-1BM680
44
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES A Transmit Channel Conguration Registers
30002
—
TXHR_AA
Transmit Half
Rate Selec-
tion Bit, Bank
A, Channel A.
When TXHR =
1, the trans-
mitter sam-
ples data on
the falling
edge of the
TBC clock.
When TXHR =
0, the trans-
mitter sam-
ples data on
the falling
edge of the
double rate
clock (derived
from TBC).
TXHR = 0 on
device reset.
PWRDNT_AA
Transmit Pow-
erdown Con-
trol Bit, Bank
A, Channel A.
When
PWRDNT = 1,
sections of the
transmit hard-
ware are pow-
ered down to
conserve
power.
PWRDNT = 0
on device
reset.
PE0_AA
Transmit Pre-
emphasis
Selection Bit
0, Bank A,
Channel A.
PE0, together
with PE1,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE0 = 0
on device
reset.
PE1_AA
Transmit Pre-
emphasis
Selection Bit
1, Bank A,
Channel A.
PE1, together
with PE0,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE1 = 0
on device
reset.
HAMP_AA
Transmit Half
Amplitude
Selection Bit,
Bank A, Chan-
nel A. When
HAMP = 1, the
transmit out-
put buffer volt-
age swing is
limited to half
its amplitude.
Otherwise, the
transmit out-
put buffer
maintains its
full voltage
swing. HAMP
= 0 on device
reset.
TBCKSEL_AA
Transmit Byte
Clock Selec-
tion Bit, Bank
A, Channel A.
When TBCK-
SEL = 0, the
internal XCK is
selected. Oth-
erwise, the
TBC clock is
selected.
TBCKSEL = 0
on device ser-
set.
RSVD
8B10BT_AA
Transmit 8B/
10B Encoder
Enable Bit,
Bank A, Chan-
nel A. When
8B10BT = 1,
the 8B/10B
encoder on
the transmit
path is
enabled. Oth-
erwise, it is
bypassed.
8B10BT = 0
on device
reset.
00
30012
—
TXHR_AB
Transmit Half
Rate Selec-
tion Bit, Bank
A, Channel B.
When TXHR =
1, the trans-
mitter sam-
ples data on
the falling
edge of the
TBC clock.
When TXHR =
0, the trans-
mitter sam-
ples data on
the falling
edge of the
double rate
clock (derived
from TBC).
TXHR = 0 on
device reset.
PWRDNT_AB
Transmit Pow-
erdown Con-
trol Bit, Bank
A, Channel B.
When
PWRDNT = 1,
sections of the
transmit hard-
ware are pow-
ered down to
conserve
power.
PWRDNT = 0
on device
reset.
PE0_AB
Transmit Pre-
emphasis
Selection Bit
0, Bank A,
Channel B.
PE0, together
with PE1,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE0 = 0
on device
reset.
PE1_AB
Transmit Pre-
emphasis
Selection Bit
1, Bank A,
Channel B.
PE1, together
with PE0,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE1 = 0
on device
reset.
HAMP_AB
Transmit Half
Amplitude
Selection Bit,
Bank A, Chan-
nel B. When
HAMP = 1, the
transmit out-
put buffer volt-
age swing is
limited to half
its amplitude.
Otherwise, the
transmit out-
put buffer
maintains its
full voltage
swing. HAMP
= 0 on device
reset.
TBCKSEL_AB
Transmit Byte
Clock Selec-
tion Bit, Bank
A, Channel B.
When TBCK-
SEL = 0, the
internal XCK is
selected. Oth-
erwise, the
TBC clock is
selected.
TBCKSEL = 0
on device ser-
set.
RSVD
8B10BT_AB
Transmit 8B/
10B Encoder
Enable Bit,
Bank A, Chan-
nel B. When
8B10BT = 1,
the 8B/10B
encoder on
the transmit
path is
enabled. Oth-
erwise, it is
bypassed.
8B10BT = 0
on device
reset.
00
30022
—
TXHR_AC
Transmit Half
Rate Selec-
tion Bit, Bank
A, Channel C.
When TXHR =
1, the trans-
mitter sam-
ples data on
the falling
edge of the
TBC clock.
When TXHR =
0, the trans-
mitter sam-
ples data on
the falling
edge of the
double rate
clock (derived
from TBC).
TXHR = 0 on
device reset.
PWRDNT_AC
Transmit Pow-
erdown Con-
trol Bit, Bank
A, Channel C.
When
PWRDNT = 1,
sections of the
transmit hard-
ware are pow-
ered down to
conserve
power.
PWRDNT = 0
on device
reset.
PE0_AC
Transmit Pre-
emphasis
Selection Bit
0, Bank A,
Channel C.
PE0, together
with PE1,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE0 = 0
on device
reset.
PE1_AC
Transmit Pre-
emphasis
Selection Bit
1, Bank A,
Channel C.
PE1, together
with PE0,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE1 = 0
on device
reset.
HAMP_AC
Transmit Half
Amplitude
Selection Bit,
Bank A, Chan-
nel C. When
HAMP = 1, the
transmit out-
put buffer volt-
age swing is
limited to half
its amplitude.
Otherwise, the
transmit out-
put buffer
maintains its
full voltage
swing. HAMP
= 0 on device
reset.
TBCKSEL_AC
Transmit Byte
Clock Selec-
tion Bit, Bank
A, Channel C.
When TBCK-
SEL = 0, the
internal XCK is
selected. Oth-
erwise, the
TBC clock is
selected.
TBCKSEL = 0
on device ser-
set.
RSVD
8B10BT_AC
Transmit 8B/
10B Encoder
Enable Bit,
Bank A, Chan-
nel C. When
8B10BT = 1,
the 8B/10B
encoder on
the transmit
path is
enabled. Oth-
erwise, it is
bypassed.
8B10BT = 0
on device
reset.
00
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