參數(shù)資料
型號： ORT82G5-1BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 60/110頁
文件大?。?/td> 1459K
代理商： ORT82G5-1BM680
Lattice Semiconductor
53
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7 Default
Value
SERDES B Receive Channel Conguration Registers
30103
—
RXHR_BA
Receive Half Rate
Selection Bit, Bank B,
Channel A. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_BA
Receiver Power
Down Control Bit,
Bank B, Channel A.
When PWRDNR = 1,
sections of the
receive hardware are
powered down to
conserve power.
PWRDNR = 0 on
device reset.
SDOVRIDE_BA
Receive Signal
Detect Alarm Over-
ride Bit, Bank B,
Channel A. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
8B10BR_BA
Receive 8B/10B
Decoder Enable Bit,
Bank B, Channel A.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path is
enabled. Otherwise,
it is bypassed.
8B10BR = on device
reset.
LINKSM_BA
Link State Machine
Enable Bit, Bank B,
Channel A. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
———
20
30113
—
RXHR_BB
Receive Half Rate
Selection Bit, Bank B,
Channel B. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_BB
Receiver Power
Down Control Bit,
Bank B, Channel B.
When PWRDNR = 1,
sections of the
receive hardware are
powered down to
conserve power.
PWRDNR = 0 on
device reset.
SDOVRIDE_BB
Receive Signal
Detect Alarm Over-
ride Bit, Bank B,
Channel B. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
8B10BR_BB
Receive 8B/10B
Decoder Enable Bit,
Bank B, Channel B.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path is
enabled. Otherwise,
it is bypassed.
8B10BR = on device
reset.
LINKSM_BB
Link State Machine
Enable Bit, Bank B,
Channel B. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
———
20
30123
—
RXHR_BC
Receive Half Rate
Selection Bit, Bank B,
Channel C. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_BC
Receiver Power
Down Control Bit,
Bank B, Channel C.
When PWRDNR = 1,
sections of the
receive hardware are
powered down to
conserve power.
PWRDNR = 0 on
device reset.
SDOVRIDE_BC
Receive Signal
Detect Alarm Over-
ride Bit, Bank B,
Channel C. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
8B10BR_BC
Receive 8B/10B
Decoder Enable Bit,
Bank B, Channel C.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path is
enabled. Otherwise,
it is bypassed.
8B10BR = on device
reset.
LINKSM_BC
Link State Machine
Enable Bit, Bank B,
Channel C. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
———
20
30133
—
RXHR_BD
Receive Half Rate
Selection Bit, Bank B,
Channel D. When
RXHR = 1, the
RBC[1:0] clocks are
issued at half the
scheduled rate of the
reference clock.
RXHR = 0 on device
reset.
PWRDNR_BD
Receiver Power
Down Control Bit,
Bank B, Channel D.
When PWRDNR = 1,
sections of the
receive hardware are
powered down to
conserve power.
PWRDNR = 0 on
device reset.
SDOVRIDE_BD
Receive Signal
Detect Alarm Over-
ride Bit, Bank B,
Channel D. When
SDOVRIDE = 1, the
energy detector out-
put from the receiver
is masked. Thus,
when there is no
receive data, the
powerdown function
is disabled and the
corresponding SDON
alarm is suppressed.
SDOVRIDE = 1 on
device reset.
8B10BR_BD
Receive 8B/10B
Decoder Enable Bit,
Bank B, Channel D.
When 8B10BR = 1,
the 8B/10B decoder
on the receive path is
enabled. Otherwise,
it is bypassed.
8B10BR = on device
reset.
LINKSM_BD
Link State Machine
Enable Bit, Bank B,
Channel D. When
LINKSM = 1, the
receiver link state
machine is enabled.
Otherwise, the link
state machine is dis-
ables. LINKSM = 0
on device reset.
———
20
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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