參數(shù)資料
型號(hào)： ORT82G5-1BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁(yè)數(shù)： 63/110頁(yè)
文件大小： 1459K
代理商： ORT82G5-1BM680
56
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
* FMPU_SYNMODE_xx[0:1]
00 = No channel alignment
10 = Twin channel alignment
01 = Quad channel alignment
11 = 8 channel alignment
SCHAR_CHAN[0:1]
00 = Channel BA
10 = Channel BB
01 =Channel BC
11 = Channel BD
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
Control Registers B
30900
B0
ENBYSYNC_B
A
1 = Byte Align-
ments bank B,
channelA
ENBYSYNC_B
B
1 = Byte Align-
ments bank B,
channel B
ENBYSYNC_B
C
1 = Byte Align-
ments bank B,
channel C
ENBYSYNC_B
D
1 = Byte Align-
ments bank B,
channel D
LCKREFN_BA
0 = Lock
receiver to ref.
clock
1 = Lock
receiver to data
for bank B
channel A
LCKREFN_BB
0 = Lock
receiver to ref.
clock
1 = Lock
receiver to data
for bank B
channel B
LCKREFN_BC
0 = Lock
receiver to ref.
clock
1 = Lock
receiver to data
for bank B
channel C
LCKREFN_BD
0 = Lock
receiver to ref.
clock
1 = Lock
receiver to data
for bank B
channel D
00
30901
B1
LOOPENB_BA
Enable loop-
back mode for
bank B, chan-
nel A
LOOPENB_BB
Enable loop-
back mode for
bank B, chan-
nel B
LOOPENB_BC
Enable loop-
back mode for
bank B, chan-
nel C
LOOPENB_BD
Enable loop-
back mode for
bank B, chan-
nel D
NOWDALIGN_
BA
Defeats deMUX
alignment for
bank B, chan-
nel A
NOWDALIGN_
BB
Defeats deMUX
alignment for
bank B, chan-
nel B
NOWDALIGN_
BC
Defeats deMUX
alignment for
bank B, chan-
nel C
NOWDALIGN_
BD
Defeats deMUX
alignment for
bank B, chan-
nel D
00
30902
B2
Reserved for future use
30903
B3
Reserved for future use
30910
B4
DOWDALIGN_
BA
Force new
deMUX word
alignment for
bank B, chan-
nel A
DOWDALIGN_
BB
Force new
deMUX word
alignment for
bank B, chan-
nel B
DOWDALIGN
_BC
Force new
deMUX word
alignment for
bank B, chan-
nel C
DOWDALIGN_
BD
Force new
deMUX word
alignment for
bank B, chan-
nel D
FMPU_STR_E
N_BA
Enable align-
ment function
for channel BA
FMPU_STR_E_
BB
Enable align-
ment function
for channel BB
FMPU_STR_E
N_BC
Enable align-
ment function
for channel BC
FMPU_STR_E
N_BD
Enable align-
ment function
for channel BD
00
30911
B5* FMPU_SYNMODE_BA[0:1]
Sync mode for BA
FMPU_SYNMODE_BB[0:1]
Sync mode for BB
FMPU_SYNMODE_BC[0:1]
Sync mode for BC
FMPU_SYNMODE_BD[0:1]
Sync mode for BD
00
30912
B6
Reserved for future use
30913
B7
Reserved for future use
30920
B8
FMPU_RESYN
C1_BA
Resync a single
channel, BA.
Write a 0, then
write a 1.
FMPU_RESYN
C1_BB
Resync a single
channel, BB.
Write a 0, then
write a 1.
FMPU_RESYN
C1_BC
Resync a single
channel, BC.
Write a 0, then
write a 1.
FMPU_RESYN
C1_BD
Resync a single
channel, BD.
Write a 0, then
write a 1.
FMPU_RESYN
C2_B1
Resync 2 chan-
nels, BA and
BB.
Write a 0, then
write a 1.
FMPU_RESYN
C2_B2
Resync 2 chan-
nels, BC and
BD.
Write a 0, then
write a 1.
FMPU_RESYN
C4_B
Resync 4 chan-
nels B[A:D].
Write a 0, then
write a 1.
XAUI_MODE B
Controls use of
XAUI link state
machine vs.
SERDES link
State machine
for bank B
00
30921
B9
NOCHALGN B
Bypass chan-
nel alignment
deMUXed data
directly to FPGA
for bank B
Reserved for future use
00
30922
B10
Reserved for future use
30923
B11
Reserved for future use
30930
B12
Reserved for future use
30931
B13
Reserved for future use
30932
B14
Reserved for future use
30933
B15
Reserved for future use
SCHAR_CHAN[0:1]
Select channel to test
SCHAR_TXSEL
1=Select TX
option
0=Select RX
option
SCHAR_ENA
1=Enable Char-
acterization of
SERDES B
00
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參數(shù)描述
ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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