參數(shù)資料
型號： ORT82G5-1BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 54/110頁
文件大?。?/td> 1459K
代理商： ORT82G5-1BM680
48
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES A Global Control Register (Acts on Channels A, B, C, and D)
30005
—
GPRBS_A
Global Enable.
The GPRBS bit
globally enables
the PRBS gen-
erators and
checkers all
four channels of
SERDES A
when GPRBS =
1. GPRBS = 0
on device reset.
GMASK_A
Global Mask.
The GMASK
globally masks
all the channel
alarms of SER-
DES A when
GMASK = 1.
This prevents
all the transmit
and receive
alarms from
generating an
interrupt.
GMASK = 1 on
device reset.
GSWRST_A
RESET Func-
tion. The
GSWRST bit pro-
vides the same
function as the
hardware reset
for the transmit
and receive sec-
tions of all four
channels of
ASERDES A,
except that the
device congura-
tion settings are
not affected when
GSWRST is
asserted.
GSWRST = 0 on
device reset. This
is not a self-clear-
ing bit. Once set,
it must be cleared
by writing a 0 to it.
GPWRDNT_A
Powerdown
Transmit Func-
tion. When
GPWRDNT = 1,
sections of the
transmit hard-
ware for all four
channels of
SERDES A are
powered down
to conserve
power.
GPWRDNT = 0
on device reset.
GPWRDNR_A
Powerdown
Receive Func-
tion. When
GPWRDNR =
1, sections of
the receive
hardware for all
four channels of
SERDES A are
powered down
to conserve
power.
GPWRDNR = 0
on device reset.
GTRISTN_
A
Active-Low
TRISTN
Function.
When
GTRISTN =
0, the
CMOS out-
put buffers
for SER-
DES A are
3-stated.
GTRISTN =
1 on device
reset.
—
GTESTEN_A
Test Enable
Control. When
GTESTEN = 1,
the transmit
and receive
sections of all
four channels
of SERDES A
are placed in
test mode.
GTESTEN = 0
on device
reset.
44
30006
—
TestMode
—
RSVD
00
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ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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