
NCP5322A
http://onsemi.com
27
5. MOSFET & Heatsink Selection
The IPB05N03L from Infineon is chosen for both the
control and synchronous MOSFET due to its low R
DS(on)
and low gate
–
charge requirements. The following
parameters are derived from the IPB05N03L data sheet:
Rds
ON
= 3.9 m
@ 10 V
Q
SWITCH
= 25 nC
Q
RR
= 45 nC
Q
OSS
= 35 nC
Vf
diode
= 0.86 V @ 25 A
θ
JC
= 1.0
°
C/W
NCP5322A Parameters:
i
G
= 1.5 A
V
G
= 10 V
t_nonoverlap = 65 ns
The RMS value of the current in the control MOSFET is
calculated from Equation 20 and the previously derived
values for D, I
LMAX
, and I
LMIN
at the converter
’
s maximum
output current:
0.36
[(26.52
26.5
18.5
18.52) 3]1 2
(20)
IRMS,CNTL
[D
(ILo,MAX2
ILo,MIN2) 3]1 2
ILo,MAX
ILo,MIN
8.15 ARMS
Equation 19 is used to calculate the power dissipation of
the control MOSFET:
PD,CONTROL
(IRMS,CNTL2
QswitchIg
VIN
RDS(on))
VIN
(VIN
(ILo,MAX
(Qoss2
fSW)
QRR
fSW)
fSW)
(19)
(8.152ARMS
(26.5 A
3.9 m )
25 nC 1.5 A
12 V
220 kHz)
(35 nC 2
12 V
220 kHz)
(12 V
45 nC
220 kHz)
0.26 W
1.60 W
1.17 W
0.05 W
0.12 W
The RMS value of the current in the synchronous
MOSFET is calculated from Equation 27 and the previously
derived values for D, I
Lo,MAX
, and I
Lo,MIN
at the converter
’
s
maximum output current:
(27)
IRMS,SYNCH
(ILo,MAX2
[(1
D)
ILo,MAX
(26.52
ILo,MIN
ILo,MIN2) 3]1 2
18.52) 3]1 2
[(1
0.13)
26.5
18.5
21.1 ARMS
Equation 26 is used to calculate the power dissipation of
the synchronous MOSFET:
PD,SYNCH
(IRMS,SYNCH2
(Vfdiode
IO,MAX2
RDS(on))
t_nonoverlap
fSW)
(26)
(21.12ARMS
(0.86 V
3.9 m )
45 A 2
65 ns
220 kHz)
1.74 W
0.28 W
2.02 W
Equation 28 is used to calculate the heat sink thermal
impedances necessary to maintain less than the specified
maximum junction temperatures at 60
°
C ambient:
CNTL
(125
60 C) 1.6 W
1.0 C W
40 C W
SYNCH
(125
60 C) 2.02 W
1.0 C W
31 C W
If board area permits, a cost effective heatsink could be
formed by using a TO
–
263 mounting pad of at least 1.5 in
2
for the upper MOSFET and 2.5 in
2
for the lower MOSFET
on a single
–
sided, 1 oz. copper PCB. The total required pad
area would be slightly less if the area were divided evenly
between top and bottom layers with multiple thermal vias
joining the two areas. To conserve board space, AAVID
offers clip
–
on heatsinks for TO
–
220 thru
–
hole packages.
Examples of these heatsinks include #577002 (1
″ ×
0.75
″ ×
0.25
″
, 33
°
C/W at 2 W) and #591302 (0.75
″ ×
0.5
″ ×
0.5
″
,
29
°
C/W at 2 W).
6. Adaptive Voltage Positioning
First, to achieve the 220 kHz switching frequency, use
Figure 4 to determine that a 65 k
resistor is needed for
R
OSC
. Then, use Figure 5 to find the V
FB
bias current at the
corresponding value of R
OSC
. In this example, the 65 k
R
OSC
resistor results in a V
FB
bias current of approximately
5.0
μ
A. Knowing the V
FB
bias current, one can calculate the
required values for R
FBK1
and R
DRP
using Equations 29
through 31.
The no
–
load position is easily set using Equation 29:
RFBK1
VNO
–
LOADIBIASVFB
+30 mV 5.0 A
6.04 k
(29)
For inductive current sensing, the designer must calculate
the inductor
’
s resistance (R
L
) and approximate any
resistance added by the circuit board (R
PCB
). We found the
inductor
’
s nominal resistance in Section 2 (0.82 m
). In this
example, we approximate 0.50 m
for the circuit board
resistance (R
PCB
). With this information, Equation 30 can
be used to calculate the increase at the V
DRP
pin at full load:
VDRP
IO,MAX
45 A
(RL
RPCB)
0.50 m )
GVDRP
(1.03 m
3.3 V V
227 mV
(30)
R
DRP1
can then be calculated from Equation 31: