參數(shù)資料
型號: NCP5322A
廠商: ON SEMICONDUCTOR
英文描述: TWO-PHASE BUCK CONTROLLER WITH INTEGRATED GATE DRIVERS AND 5-BIT DAC
中文描述: 兩相降壓控制器,它集成柵極驅(qū)動(dòng)器和5位DAC
文件頁數(shù): 19/32頁
文件大小: 1091K
代理商: NCP5322A
NCP5322A
http://onsemi.com
19
IC,MAX
ILo,MAX
IIN,AVG
(6)
IC,MIN
ILo,MIN
IIN,AVG
(7)
I
Lo,MAX
is the maximum output inductor current:
ILo,MAX
IO,MAX2
ILo2
(8)
I
Lo,MIN
is the minimum output inductor current:
ILo,MIN
IO,MAX2
ILo2
(9)
I
Lo
is the peak
to
peak ripple current in the output
inductor of value Lo:
ILo
(VIN
VOUT)
D (Lo
fSW)
(10)
For the two
phase converter, the input capacitor(s) RMS
current is then:
ICIN,RMS
[2D
(IC,MIN2
IC,MIN
IC,IN
IC,IN23)
IIN,AVG2
(1
2D)]1 2
(11)
Select the number of input capacitors (N
IN
) to provide the
RMS input current (I
CIN,RMS
) based on the RMS ripple
current rating per capacitor (I
RMS,RATED
):
NIN
ICIN,RMSIRMS,RATED
(12)
For a two
phase converter with perfect efficiency (
η
= 1),
the worst case input ripple
current will occur when the
converter is operating at a 25% duty cycle. At this operating
point, the parallel combination of input capacitors must
support an RMS ripple current equal to 25% of the
converter
s DC output current. At other duty cycles, the
ripple
current will be less. For example, at a duty cycle of
either 10% or 40%, the two
phase input ripple
current will
be approximately 20% of the converter
s DC output current.
In general, capacitor manufacturers require derating to the
specified ripple
current based on the ambient temperature.
More capacitors will be required because of the current
derating. The designer should be cognizant of the ESR of the
input capacitors. The input capacitor power loss can be
calculated from:
PCIN
ICIN,RMS2
ESR_per_capacitor NIN
(13)
Low ESR capacitors are recommended to minimize losses
and reduce capacitor heating. The life of an electrolytic
capacitor is reduced 50% for every 10
°
C rise in the
capacitor
s temperature.
4. Input Inductor Selection
The use of an inductor between the input capacitors and
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
inrush currents will reduce the expected life of the input
capacitors. The inductor
s limiting effect on the input
current slew rate becomes increasingly beneficial during
load transients.
The worst case input current slew rate will occur during
the first few PWM cycles immediately after a step
load
change is applied as shown in Figure 16. When the load is
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
instantaneously so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (I
O,MAX
), the per capacitor ESR of the output
capacitors (ESR
OUT
), and the number of the output
capacitors (N
OUT
) as shown in Figure 16. Assuming the load
current is shared equally between the two phases, the output
voltage at full, transient load will be:
VOUT,FULL
LOAD
VOUT,NO
LOAD
(14)
(IO,MAX2)
ESROUTNOUT
+
+
Vi
12 V
Li
TBD
Ci
3
×
16SP270
ESR
Ci
18 m/3 = 6.0 m
Q2
Q1
Lo
700 nH
ESR
Co
13 m/7 = 1.9 m
22.5 u(t)
Co
7
×
16MBZ1500M10X20
Vi(t = 0) = 12 V
SWNODE
Vo(t = 0) = 1.630 V
V
Ci
I
Lo
V
OUT
I
Li
MAX dI/dt occurs in
first few PWM cycles.
Figure 16. Calculating the Input Inductance
+
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