參數(shù)資料
型號(hào)： NCP5322A
廠商： ON SEMICONDUCTOR
英文描述： TWO-PHASE BUCK CONTROLLER WITH INTEGRATED GATE DRIVERS AND 5-BIT DAC
中文描述： 兩相降壓控制器，它集成柵極驅(qū)動(dòng)器和5位DAC
文件頁數(shù)： 13/32頁
文件大?。?/td> 1091K
代理商： NCP5322A
NCP5322A
http://onsemi.com
13
Enhanced V
2
responds to disturbances in V
CORE
by
employing both
“
slow
”
and
“
fast
”
voltage regulation. The
internal error amplifier performs the slow regulation.
Depending on the gain and frequency compensation set by
the amplifier
’
s external components, the error amplifier will
typically begin to ramp its output to react to changes in the
output voltage in 1
–
2 PWM cycles. Fast voltage feedback is
implemented by a direct connection from V
CORE
to the
non
–
inverting pin of the PWM comparator via the
summation with the inductor current, internal ramp, and
Offset. A rapid increase in load current will produce a
negative offset at V
CORE
and at the output of the summer.
This will cause the PWM duty cycle to increase almost
instantly. Fast feedback will typically adjust the PWM duty
cycle in 1 PWM cycle.
As shown in Figure 10, an internal ramp (nominally 125 mV
at a 50% duty cycle) is added to the inductor current ramp
at the positive terminal of the PWM comparator. This
additional ramp compensates for propagation time delays
from the current sense amplifier (CSA), the PWM
comparator, and the MOSFET gate drivers. As a result, the
minimum ON time of the controller is reduced and lower
duty cycles may be achieved at higher frequencies. Also, the
additional ramp reduces the reliance on the inductor current
ramp and allows greater flexibility when choosing the output
inductor and the R
CSn
C
CSn
(n = 1 or 2) time constant of the
feedback components from V
CORE
to the CSn pin.
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. When the average output
current is zero, the COMP pin will be:
VCOMP
VOUT@ 0 A
Int_Ramp
Channel_Startup_Offset
GCSA
Ext_Ramp 2
Int_Ramp is the
“
partial
”
internal ramp value at the
corresponding duty cycle, Ext_Ramp is the peak
–
to
–
peak
external steady
–
state ramp at 0 A, G
CSA
is the Current Sense
Amplifier Gain (nominally 3.5 V/V), and the Channel
Startup Offset is typically 0.40 V. The magnitude of the
Ext_Ramp can be calculated from:
Ext_Ramp
D
(VIN
VOUT) (RCSn
CCSn
fSW)
For example, if V
OUT
at 0 A is set to 1.630 V with AVP
and the input voltage is 12.0 V, the duty cycle (D) will be
1.630/12.0 or 13.6%. Int_Ramp will be 125 mV
13.6/50 =
34 mV. Realistic values for R
CSn
, C
CSn
and f
SW
are 60 k
,
0.01
μ
F, and 220 kHz
using these and the previously
mentioned formula, Ext_Ramp will be 10.6 mV.
VCOMP
1.630 V
3.5 V V
2.083 Vdc.
0.40 V
10.6 mV 2
34 mV
If the COMP pin is held steady and the inductor current
changes, there must also be a change in the output voltage.
Or, in a closed loop configuration when the output current
changes, the COMP pin must move to keep the same output
voltage. The required change in the output voltage or COMP
pin depends on the scaling of the current feedback signal and
is calculated as:
V
RS
GCSA
IOUT.
The single
–
phase power stage output impedance is:
Single Stage Impedance
VOUT
IOUT
RS
GCSA
The multi
–
phase power stage output impedance is the
single
–
phase output impedance divided by the number of
phases. The output impedance of the power stage determines
how the converter will respond during the first few
microseconds of a transient before the feedback loop has
repositioned the COMP pin.
The peak output current can be calculated from:
IOUT,PEAK
(VCOMP
VOUT
Offset) (RS
GCSA)
Figure 11 shows the step response of the COMP pin at a
fixed level. Before T1 the converter is in normal steady state
operation. The inductor current provides a portion of the
PWM ramp through the Current Sense Amplifier. The PWM
cycle ends when the sum of the current ramp, the
“
partial
”
internal ramp voltage signal and Offset exceed the level of
the COMP pin. At T1 the output current increases and the
output voltage sags. The next PWM cycle begins and the
cycle continues longer than previously while the current
signal increases enough to make up for the lower voltage at
the V
FB
pin and the cycle ends at T2. After T2 the output
voltage remains lower than at light load and the average
current signal level (CSn output) is raised so that the sum of
the current and voltage signal is the same as with the original
load. In a closed loop system the COMP pin would move
higher to restore the output voltage to the original level.
SWNODE
V
FB
(V
OUT
)
Internal Ramp
CSA Out w/
Exaggerated
Delays
COMP
–
Offset
CSA Out + Ramp + CS
REF
T1
T2
Figure 11. Open Loop Operation
相關(guān)PDF資料
PDF描述
NCP5322ADW TWO-PHASE BUCK CONTROLLER WITH INTEGRATED GATE DRIVERS AND 5-BIT DAC
NCP5322ADWR2 STATIC PROTECTION RoHS Compliant: Yes
NCP5332ADW Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC
NCP5332ADWR2 Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC
NCP5332A Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NCP5322A/D 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase Buck Controller with integrated Gate Drivers and 5-Bit DAC
NCP5322A_07 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC
NCP5322ADW 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
NCP5322ADWG 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC
NCP5322ADWR2 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
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