參數資料
型號： NCP5322A
廠商： ON SEMICONDUCTOR
英文描述： TWO-PHASE BUCK CONTROLLER WITH INTEGRATED GATE DRIVERS AND 5-BIT DAC
中文描述： 兩相降壓控制器，它集成柵極驅動器和5位DAC
文件頁數： 20/32頁
文件大?。?/td> 1091K
代理商： NCP5322A
NCP5322A
http://onsemi.com
20
When the control MOSFET (Q1 in Figure 16) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as:
VLo
VIN
VIN
VOUT,FULL
–
LOAD
VOUT,NO
–
LOAD
(IO,MAX2)
(15)
ESROUTNOUT
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from:
dILodt
VLoLo
(16)
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors (
V
Ci
) is determined by the number of input
capacitors (N
IN
), their per capacitor ESR (ESR
IN
), and the
current in the output inductor according to:
VCi
ESRINNIN
ESRINNIN
dILodt
dILodt
tON
D fSW
(17)
Before the load is applied, the voltage across the input
inductor (V
Li
) is very small
–
the input capacitors charge to
the input voltage, V
IN
. After the load is applied the voltage
drop across the input capacitors,
V
Ci
, appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from:
LiMIN
VLi
VCi
dIINdtMAX
dIINdtMAX
(18)
dI
IN
/dt
MAX
is the maximum allowable input current slew
rate.
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very
“
stiff
”
and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer
’
s data
sheets are worst case high limits. In reality input voltage
“
sag,
”
lower capacitor ESRs, and stray inductance will help
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating the
magnetic. Also, for an inexpensive iron powder core, such
as the
–
26 or
–
52 from Micrometals, the inductance
“
swing
”
with DC bias must be taken into account
–
inductance will
decrease as the DC input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
5. MOSFET & Heatsink Selection
Power dissipation, package size, and thermal solution
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power dissipation.
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
at the highest ambient temperature. Power dissipation has two
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
non
–
overlap time of the gate drivers.
For the upper or control MOSFET, the power dissipation
can be approximated from:
PD,CONTROL
(ILo,MAX
(Qoss2
(IRMS,CNTL2
QswitchIg
VIN
fSW)
RDS(on))
VIN
(VIN
fSW)
QRR
fSW)
(19)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the losses associated with
the
control and synchronous
MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous
MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
Where I
RMS,CNTL
is the RMS value of the trapezoidal
current in the control MOSFET:
(20)
IRMS,CNTL
[D
(ILo,MAX2
ILo,MIN2) 3]1 2
ILo,MAX
ILo,MIN
I
Lo,MAX
is the maximum output inductor current:
ILo,MAX
IO,MAX2
ILo2
(21)
I
Lo,MIN
is the minimum output inductor current:
ILo,MIN
IO,MAX2
I
O,MAX
is the maximum converter output current.
D is the duty cycle of the converter:
ILo2
(22)
D
VOUTVIN
(23)
I
Lo
is the peak
–
to
–
peak ripple current in the output
inductor of value Lo:
ILo
(VIN
VOUT)
D (Lo
fSW)
(24)
R
DS(on)
is the ON resistance of the MOSFET at the
applied gate drive voltage.
Q
switch
is the post gate threshold portion of the
gate
–
to
–
source charge plus the gate
–
to
–
drain charge. This
may be specified in the data sheet or approximated from the
gate
–
charge curve as shown in the Figure 17.
Qswitch
Qgs2
Qgd
(25)
相關PDF資料
PDF描述
NCP5322ADW TWO-PHASE BUCK CONTROLLER WITH INTEGRATED GATE DRIVERS AND 5-BIT DAC
NCP5322ADWR2 STATIC PROTECTION RoHS Compliant: Yes
NCP5332ADW Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC
NCP5332ADWR2 Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC
NCP5332A Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC
相關代理商/技術參數
參數描述
NCP5322A/D 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase Buck Controller with integrated Gate Drivers and 5-Bit DAC
NCP5322A_07 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC
NCP5322ADW 功能描述:DC/DC 開關控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK
NCP5322ADWG 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC
NCP5322ADWR2 功能描述:DC/DC 開關控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK
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