參數(shù)資料
型號(hào)： NCN6804MNR2G
廠(chǎng)商： ON Semiconductor
文件頁(yè)數(shù)： 8/25頁(yè)
文件大?。?/td> 0K
描述： IC SMART CARD DUAL W/SPI 32-QFN
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 智能卡
接口： 4 線(xiàn) SPI 串行
電源電壓： 2.7 V ~ 5.5 V
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN（5x5）
包裝： 剪切帶 (CT)
安裝類(lèi)型： 表面貼裝
其它名稱(chēng)： NCN6804MNR2GOSCT
NCN6804
http://onsemi.com
16
LOGIC AND
LEVEL SHIFT
Q4
Q3
Q2
R2
18 k
Q5
GND
CRD_VCC
13
CRD_IO
20
CRD_VCC
CARD ENABLE
POR
SEQ 1
200 ns
Q1
R1
18 k
EN_RPU
6
I/O
1
VCC
9
VCC
PMOS
U1
VCC
Q5
GND
SYNC
MOSI/b3
MOSI/b2
From MOSI
decoding
Figure 8. Basic I/O Internal Circuit
The transaction is valid when the Chip Select pin is Low,
the I/O signal being Open Drain or Totem Pole on either
sides.
Since the device can operate either in a single or a multiple
card system provisions have been made to avoid CRD_IOA
or B current overload. Depending upon the selected mode of
operation (Async. or Sync), the card I/O line is respectively
connected to either I/O Pin 25, or to the MOSI register byte
bit 2. On the other hand, the logic level present at the card I/O
is feedback to the microcontroller via the MISO register
bit 3. The logic levels present at Pin 31 (EN_RPU) controls
the connection of the internal pullup as depicted Table 6.
Table 6. I/O PULLUP RESISTOR TABLE
EN_RPU
I/O Pullup Resistor
Device Operation
Low
Open, 18 kW
Disconnected
Applicable in the
Multidevice Mode
Case
High
Internal 18 kW Pullup
Active
Single Device
Mode
NOTE: 18 kW typical value
Figure 9. Typical I/O rise & fall time (CRD_IOA or B/
Cout > 30 pF and opendrain)
Interrupt
When the system is powered up, the INT Pin is set to
HIGH upon Power On Reset (POR) signal. The interrupt
Pin 24 is forced LOW when a card is inserted or extracted
in either of the external ports, or when a fault is developed
across the CRD_VCC output voltage A or B. This signal is
neither combined with CS signal, nor with the chip address.
The INT signal is clear to HIGH upon one of the conditions
Table 7.
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