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參數(shù)資料
| 型號(hào)： | NCN6804MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 20/25頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SMART CARD DUAL W/SPI 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 智能卡 |
| 接口： | 4 線 SPI 串行 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6804MNR2GOSCT |
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NCN6804
http://onsemi.com
4
PIN FUNCTION AND DESCRIPTION
PIN
Name
Type
Description
1
S1
I
Address pin (Chip Identification pin) – allows having in parallel up to 2 NCN6804 devices (4 inter-
faces) managed by 1 Chip Select pin only (CS) – multiple interface application case. When one dual
interface only is used this pin can be connected to GROUND.
2, 23
CRD_DETA,
CRD_DETB
I
The signal coming from the external card connector is used to detect the presence of the card. A
builtin pullup low current source biases this pin HIGH, making it active LOW, assuming one side of
the external switch is connected to ground. A builtin digital filter protects the system against voltage
spikes present on this pin. The polarity of the signal is programmable by the MOSI message; refer to
Table 2. On the other hand, the meaning of the feedback message contained in the MISO register bit
b4, depends upon the SPI mode of operation as defined here below:
SPI Normal Mode: The MISO bit b4 is HIGH when a card is inserted, whatever be the polarity of the
card detect switch.
SPI Special Mode: The MISO bit b4 copies the logic state of the card detect switch as depicted here
below, whatever be the polarity of the switch used to handle the detection:
CRD_DET = LOW => MISO/b4 = LOW
CRD_DET = HIGH => MISO/b4 = HIGH
In both cases, the chip must be programmed to control the right logic state (Table 2). Since the bias
current supplied by the chip is very low, typically 5.0 mA, care must be observed to avoid low imped-
ance or cross coupling when this pin is in the Open state.
3, 22
CRD_C4A,
CRD_C4B
O
Auxiliary mixed analog/digital line to handle synchronous card connected when used to the card pin
C4. An accelerator circuit makes sure the output positive going rise time is fully within the ISO/EMV
specifications.
4, 21
CRD_C8A,
CRD_C8B
O
Auxiliary mixed analog/digital line to handle synchronous card connected when used to the card pin
C8. An accelerator circuit makes sure the output positive going rise time is fully within the ISO/EMV
specifications.
5, 20
CRD_IOA,
CRD_IOB
I/O
This pin handles the connection to the serial I/O pin of the card connector. A bidirectional level
translator adapts the serial I/O signal between the card and the mC. An internal active pull down
device forces this pin to GROUND during either the CRD_VCC start up sequence, or when
CRD_VCC = 0V. The output current is internally limited to 15mA. When operating in a synchronous
mode I/O is transmitted through the SPI bus (MOSI bit b2) to CRD_I/O. In that case I/O is disconnec-
ted and no longer used.
6, 19
CRD_RSTA,
CRD_RSTB
O
This pin is connected to the RESET pin of the card connector. A level translator adapts the RESET
signal from the mC (through the SPI bus) to the external card. The output current is internally limited
to 15mA. The CRD_RST is validated when CS = LOW, and is hard wired to GROUND by and intern-
al active pull down circuit when the card is deactivated.
7, 18
CRD_CLKA,
CRD_CLKB
O
Clock pin connected to the card pin C3. An internal active pull down device forces this pin to
GROUND during the CRD_VCC start up sequence, or when CRD_VCC = 0V. The rise and fall
slopes, either FAST or SLOW, of this signal can be programmed by the SPI bus. Refer to Table 2.
8, 17
CRD_VCCA,
CRD_VCCB
Power
Power supply to the external card (card pin C1). An external capacitor Cout = 10 mF minimum is re-
quired. In the event of a CRD_VCC undervoltage issue, the NCN6804 detects the situation and
feedback the information in the STATUS bit (MISO bit b0). The device does not take any further ac-
tion; particularly the DC/DC converter is neither stopped nor reprogrammed by the NCN6804. It is
up to the external mC to handle the situation. However, when CRD_VCC is overloaded, the NCN6804
shuts off the DC/DC converter, runs a Power Down ISO7816 sequence and reports the fault in the
STATUS register (MISO register bit b0).
9
L2A
Power
The high side of the external inductor A.
10
GNDPA
Power
DC/DC converter A power ground pin.
11
L1A
Power
The low side of the external inductor A.
12
VDDPA
Power
DC/DC converter A power supply input (Cbypass_min = 4.7 mF).
13
VDDPB
Power
DC/DC converter B power supply input (Cbypass_min = 4.7 mF).
14
L1B
Power
The low side of the external inductor B.
15
GNDPB
Power
DC/DC converter B power ground pin.
16
L2B
Power
The high side of the external inductor B.
24
INT
O
This pin is activated LOW when a card has been inserted and detected by the CRD_DETA or
CRD_DETB pins in either of the external ports. Similarly an interrupt is generated when the
CRD_VCCA or B output is overloaded, or when the card has been extracted whatever be the trans-
action status (running or stand by). The INT signal is reset to HIGH according to Table 7. On the
other hand, the pin is forced to logic HIGH when the power supply voltage VDDPA or B drops below
2 V.
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