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參數(shù)資料
| 型號： | NCN6804MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SMART CARD DUAL W/SPI 32-QFN |
| 標準包裝： | 1 |
| 應(yīng)用： | 智能卡 |
| 接口： | 4 線 SPI 串行 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6804MNR2GOSCT |
NCN6804
http://onsemi.com
5
PIN FUNCTION AND DESCRIPTION
PIN
Description
Type
Name
25
I/O
This pin is connected to an external microcontroller (mC) interface. A bidirectional level translator
adapts the serial I/O signal between the smart card and the mC. The level translator is enabled when
CS = LOW, the sub address has been selected and the system operates in the Asynchronous mode.
When a Synchronous card is in use this pin is disconnected and the data and transaction take place
through the MOSI and the MISO registers. The internal pull up resistor connected on the mC side is
activated and visible by the selected chip only.
26
CLK_IN
I
This pin (high impedance) can be connected to either the mC master clock or to a crystal oscillator
clock to drive the external smart cards. The signal is fed to the internal clock selector circuit and
translated to the CRD_CLKA or CRD_CLKB pins at either the same frequency, or divided by 2, 4 or
8, depending upon the programming mode. Refer to table 2. Synchronous case: clock managed
through the SPI bus – CLK_IN is disconnected. Note: The chip guarantees the EMV 50% Duty Cycle
when the clock divider ratio is 1/2, 1/4, or 1/8, even when the CLK_IN signal is out of the 45% to 55%
range specified by ISO and EMV specifications.
27
CS
I
This pin synchronizes and enables the SPI communication. All the NCN6804 functions, both pro-
gramming and card transaction, are disabled when CS = HIGH.
28
CLK_SPI
Clock Signal to synchronize the SPI data transfer. This clock is fully independent from the CLK_IN
signal and does not play any role with the data transaction (I/O – CRD_I/O).
29
MISO
O
Master In Slave Out: SPI Data Output from the NCN6804. This STATUS byte carries the state of the
interface, the serial transfer being achieved according to the programmed mode (Table 2), using the
same CLK_SPI signal and during the same MOSI time frame. An external 4.7 kW pull down resistor
might be necessary to avoid misunderstanding of the pin 29 voltage during the High Z state.
30
MOSI
I
Master Out Slave In: SPI Data Input from the mC. This byte contains the address of the selected chip
among the two possible (bit b6), together with the programming code for a given interface. See Table
2.
31
EN_RPU
I
This pin is used to activate the I/O internal pullup resistor such as:
EN_RPU = Low => I/O Pullup resistor disconnected
EN_RPU = High => I/O Pullup resistor connected
When two or more NCN6804 chips share the same I/O bus, one chip only shall have the internal
pullup resistor enabled to avoid any overload of the I/O line. Moreover, when Asynchronous and
Synchronous cards are handled by the interfaces, the activated I/O pullup resistor must preferably
be the one associated with the asynchronous circuit. On the other hand, since no internal pullup
bias resistor is built in the chip, pin 31 must be connected to the right voltage level to make sure the
logic function is satisfied.
32
VDD
Power
This pin is connected to the system controller power supply (Cbypass_min = 100 nF). When VDD is
below 2.5 V the CRD_VCCA or B is disabled. The NCN6804 goes into a shutdown mode.
33
GNDD
Power
Digital/analog Ground. This pin is the Exposed Pad and is the Ground for the digital/analog circuit
section. It needs to be connected to the PCB Ground.
ATTRIBUTES
Characteristics
Values
ESD protection
Human Body Model, Smart Card Pins (Card Interface Pins (Card A
and B)) (Note 1)
Human Body Model, CRD_DETA/B Pins (2, 23) (Note 1)
Human Body Model, All Other Pins (Note 1)
8 kV
4 kV
2 kV
Moisture sensitivity (Note 2) QFN32
Level 1
Flammability Rating Oxygen Index: 28 to 34
UL 94 V0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Human Body Model (HBM), R = 1500 W, C = 100 pF.
2. For additional information, see Application Note AND8003/D.
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