參數(shù)資料
型號(hào)： NCN6804MNR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 13/25頁(yè)
文件大小： 0K
描述： IC SMART CARD DUAL W/SPI 32-QFN
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 智能卡
接口： 4 線(xiàn) SPI 串行
電源電壓： 2.7 V ~ 5.5 V
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN（5x5）
包裝： 剪切帶 (CT)
安裝類(lèi)型： 表面貼裝
其它名稱(chēng)： NCN6804MNR2GOSCT
NCN6804
http://onsemi.com
20
DC/DC Operation
The power conversion is based on a full bridge structure
able to handle either step up or step down power supply (see
Figure 16). The operation is fully automatic and, beside the
output voltage programming, does not need any further
adjustment.
Figure 16. Basic DC/DC Converter
G_Q4
G_Q2
G_Q7
G_HIZ
G_Q3
G_Q1
CMD_STOP
CMD_5.0V
CMD_3.0V
CMD_1.8V
GND
22 mH
L1
GND
PWR_GND
10 mF
C2
Q2
Q7
Q4
Q6
Q5
Q3
Q1
10 mF
MIXED
LOGIC/ANALOG
BLOCK
VCC
CRD_VCC
C1
In order to achieve the 250
ms maximum time to discharge
CRD_VCCA or B to 400 mV called by the EMV
specifications, an active pull down NMOS is provided to
discharge the external CRD_VCCA/B reservoir capacitor.
This timing is guaranteed for a 10
mF maximum load
reservoir capacitor value (see Figure 4).
The system operates with a two cycle concept (all
comments are referenced to Figures 16 and 17):
1. Cycle 1 Q1 and Q4 are switched ON and the
inductor L1 is charged by the energy supplied by
the external battery. During this phase, the pair
Q2/Q3 and the pair Q5/Q6 are switched OFF. The
current flowing the two MOSFET Q1 and Q4 is
internally monitored and will be switched OFF
when the Ipeak value (depending upon the
programmed output voltage value) is reached. At
this point, Cycle 1 is completed and Cycle 2 takes
place. The ON time is a function of the battery
voltage and the value of the inductor network (L
and Zr) connected across pins 10/11. A 4 _s
timeout structure ensures the system does run in a
continuous Cycle 1 loop.
2. Cycle 2 Q2 and Q3 are switched ON and the
energy stored into the inductor L1 is dumped into
the external load through Q2. During this phase,
the pair Q1/Q4 and the pair Q5/Q6 are switched
OFF. The current flow period is constant (900 ns
typical) and Cycle 1 repeats after this time if the
CRD_VCC voltage is below the specified value.
When the output voltage reaches the specified value
(1.8 V, 3.0 V or 5.0 V), Q2 and Q3 are switched OFF
immediately to avoid over voltage on the output load. In the
meantime, the two extra NMOS Q5 and Q6 are switched ON
to fully discharge any current stored into the inductor,
avoiding ringing and voltage spikes over the system.
Figure 17 illustrates the theoretical waveforms present in
the DC/DC converter.
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