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| 型號(hào)： | NCN6804MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 10/25頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SMART CARD DUAL W/SPI 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 智能卡 |
| 接口： | 4 線 SPI 串行 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 封裝/外殼： | 32-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6804MNR2GOSCT |
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NCN6804
http://onsemi.com
18
SPI Port
The product communicates to the external micro
controller by means of a serial link using a Synchronous Port
Interface protocol, the CLK_SPI being Low or High during
the idle state. The NCN6804 is not intended to operate as a
Master controller, but executes commands coming from the
MPU.
The CLK_SPI, CS and MOSI signals are under the
microcontroller’s responsibility. The MISO signal is
generated by the NCN6804, using the CLK_SPI and CS
lines to synchronize the bits carried out by the data byte. The
with two internal registers associated with MOSI and MISO
data:
WRT_REG is a write only register dedicated to the
MOSI data.
READ_REG is a read only register dedicated to the
MISO data.
Figure 11. Basic SPI Timings and Protocol
MPU Asserts Chip Select
NCN6804 Reads Bit
MPU Reads Bit
RST_COUNTER
MOSI
SPI_CLK
CS
MISO
tclr
MPU Enables
Clock
MPU Sends Bit
NCN6001 Sends Bit
from READ_REG
When the CS line is High, no data can be written or read
on the SPI port. The two data lines become active when
CS = Low, the internal shift register is cleared and the
communication is synchronized by the negative going edge
of the CS signal. THe data presents on the MOSI line are
considered valid on the negative going edge of the CLK_SPI
clock and is transferred to the shift register on the next
positive edge of the same CLK_SPI clock.
To accommodate the simultaneous MISO transmit, an
internal logic identifies the chip address on the fly (reading
and decoding the three first bits) and validate the right data
present on the line. Consequently, the data format is MSB
first to read the first three signal as bits b5, b6 and b7. The
chip address is decoded from this logic value and validates
the chip according to the S1 pin conditions: see Figure 12.
Figure 12. Chip Address Decoding Protocol and MISO Sequence
MPU Asserts Chip Set
MISO Line = High Impedance
ADDRESS
DECODE
MOSI
SPI_CLK
CS
MISO
MPU Enables Clock
B7
B6
B5
B4
B3
B2
B1
B0
LSB
COMMAND AND CONTROL
CHIP
ADDRESS
The Chip Address is decoded on the third clock pulse.
The MISO signal is activated and data transferred
MSB
When the bit transfer is completed, the content of the internal shift register is latched on the positive going edge of the CS
signal and the NCN6804 related functions are updated accordingly.
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