
NCN6804
http://onsemi.com
22
Figure 20. Output Current Limit: Output voltage
CRD_VCC (1.8 V, 3.0 V, 5.0 V)
CRD_VCC
(V)
6
5
4
3
2
1
0
50
100
150
200
ICRD_VCC (mA)
3.0 V
5.0 V
1.8 V
On the other hand, the circuit is designed to make sure no
over current exist over the full temperature range. As a
matter of fact, the output current limit is reduced when the
temperature increases.
DCTODC Converter External PASSIF Component
Selection
To be functional the NCN6804’s DCtoDC converters
need external passive components carefully selected. The
performance and specification compliance of the NCN6804
are guaranteed by the DC/DC converter input capacitor, by
the inductor and the reservoir capacitor characteristics. The
input capacitor enables the decoupling and filtering of the
input power supply voltage (VBAT) and its value has to be
high enough to guarantee a good operating stability of the
converter. A CMS very low ESR capacitor shall be
preferably used with a minimum value of 4.7
mF
recommended, 10
mF will be preferred this will strongly
depend on how the capacitance value varies with the DC
voltage applied across the capacitor terminals (see
Figure
21). The inductor shall be sized to handle the 500 mA
peak current (Min. Isat) flowing during the DC/DC operation
and will have to offer a low parasitic series resistor in order
to
maintain
a
good
efficiency
(Ex:
Coilcraft,
1008PS223KLC). The reservoir output capacitor shall be
also ceramic surface mount capacitor with very low ESR
(lower than 50 m
W) and good temperature characteristics
(X7R type). 10
mF is the recommended capacitance value
under 5 V, 3 V and 1.8 V to get the better operating
performance with a low CRD_VCC ripple level. The CMS
capacitor shall be selected accordingly that is with a
capacitance value of 10
mF covering the range 1.8 V – 5 V
(see Figure
21). This value constitutes a good compromise
for a good CRD_VCC ripple and CRD_VCC turnon and
turnoff times.
Figure 21. Variation of the Capacitance Value of
Different CMS Capacitors with the DC Voltage
Applied Across its Terminals
CAP
ACIT
ANCE
(pF)
DC BIAS VOLTAGE (V)
10 mF, X7R, 1210, 16 V
10 mF, X5R, 1206, 16 V
10 mF, X7R,
0805, 10 V
10 mF, Y5V, 0805, 16 V
1.2E+7
1E+7
8E+6
6E+6
4E+6
2E+6
0
1.25
2.5
3.75
5
6.25
Smart Card Clock Divider
The main purpose of the built in clock generator is three
folds:
1. Adapts the voltage level shifter to cope with the
different voltages that might exist between the
MPU and the Smart Card
2. Provides a frequency division to adapt the Smart
Card operating frequency from the external clock
source.
3. Controls the clock state according to the smart
card specification.
In addition, the NCN6804 adjusts the signal coming from
the
mC to get the Duty Cycle window as defined by the
ISO78163 specification.
The byte content of the SPI port b2 and b3 fulfills the
programming functions when CS is Low as depicted
Figures
22 and
23. The clock input stage (CLOCK_IN) can
handle a 40 MHz frequency maximum signal, the divider
being capable to provide a 1:4 ratio. Of course, the ratio
must be defined by the engineer to cope with the Smart Card
considered in a given application and, in any case, the output
clock [CRD_CLKA/B] shall be limited to 20 MHz
maximum. In order to minimize the dI/dt and dV/dV
developed in the CRD_CLKA/B line, the output stage
includes a special function to adapt the slope of the clock
signal for different applications. This function is
programmed by the MOSI register (see Table
2) whatever be
the clock division.