![](http://datasheet.mmic.net.cn/ON-Semiconductor/NCN6804MNR2G_datasheet_99118/NCN6804MNR2G_8.png)
NCN6804
http://onsemi.com
8
DIGITAL INPUT/OUTPUT SECTION CLK_IN, I/O, CLK_SPI, MOSI, MISO, CS, INT, EN_RPU (40°C to +85°C)
Pin
Symbol
Rating
Min
Typ
Max
Unit
26
FCLK_IN
Input Asynchronous Clock Duty Cycle = 50%
@ VDD = 3.0 V
@ VDD = 5.0 V
30
40
MHz
26
Ftr
Ftf
Input Clock Rise time
Input Clock Fall time
2
ns
28
FCLK_SPI Input SPI clock
15
MHz
28
trspi, tfspi Input CLK_SPI Rise/Falltime
12
ns
30
trmosi,
tfmosi
Input MOSI Rise/Falltime
12
ns
29
trmiso,
tfmiso
Output MISO Rise/Falltime @ CS = 30 pF
12
ns
27
trstr, tfstr Input CS Rise/Falltime
12
ns
25
tRIO
tFIO
I/O Data Transfer Switching Time, both directions (I/O & CRD_IOA/B)
@ Cs = 30 pF
I/O Rise time (see Note 7)
I/O Fall time
0.8
ms
24
RINT
INT Pull Up Resistor
20
45
80
kW
25,26,2
7,28,30
VIH
Positive going Input High Level Voltage Threshold (CLK_IN, MOSI,
CLK_SPI, CS, EN_RPU)
0.70 * VDD
VDD
V
25,26,2
7,28,30
VIL
Negative going Input Low Level Voltage (CLK_IN, MOSI, CLK_SPI,
CS, EN RPU)
0
0.3 *VDD
V
24, 29
VOH
Output High Voltage
INT, MISO @ IOH = 10 mA (source)
VDD– 1.0
V
24, 29
VOL
Output Low Voltage
INT, MISO @ IOL = 200 mA (sink)
0.40
V
28
tdclk_spi
Delay Between 2 Consecutive CLK_SPI Burst Sequence
33
ns
25
Rpu_I/O
I/0 Pullup Resistor
12
18
24
kW
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions are not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Since a 18 kW (Typical) pullup resistor is provided by the NCN6804, the external MPU can use an Open Drain connection. On the other hand
NMOS smart cards can be used straightforward.