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參數(shù)資料
| 型號(hào)： | NAND08GR3B2AN1F |
| 廠(chǎng)商： | STMICROELECTRONICS |
| 元件分類(lèi)： | PROM |
| 英文描述： | 1G X 8 FLASH 1.8V PROM, 35 ns, PDSO48 |
| 封裝： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件頁(yè)數(shù)： | 21/57頁(yè) |
| 文件大?。?/td> | 887K |
| 代理商： | NAND08GR3B2AN1F |
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NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
28/57
Read Status Register
The device contains a Status Register which pro-
vides information on the current or previous Pro-
gram or Erase operation. The various bits in the
Status Register convey information and errors on
the operation.
The Status Register is read by issuing the Read
Status Register command. The Status Register in-
formation is present on the output data bus (I/O0-
I/O7) on the falling edge of Chip Enable or Read
Enable, whichever occurs last. When several
memories are connected in a system, the use of
Chip Enable and Read Enable signals allows the
system to poll each device separately, even when
the Ready/Busy pins are common-wired. It is not
necessary to toggle the Chip Enable or Read En-
able signals to update the contents of the Status
Register.
After the Read Status Register command has
been issued, the device remains in Read Status
Register mode until another command is issued.
Therefore if a Read Status Register command is
issued during a Random Read cycle a new Read
command must be issued to continue with a Page
Read operation.
The Status Register bits are summarized in Table
13., Status Register Bits, . Refer to Table 13. in
conjunction with the following text descriptions.
Write Protection Bit (SR7). The Write Protection
bit can be used to identify if the device is protected
or not. If the Write Protection bit is set to ‘1’ the de-
vice is not protected and program or erase opera-
tions are allowed. If the Write Protection bit is set
to ‘0’ the device is protected and program or erase
operations are not allowed.
P/E/R Controller and Cache Ready/Busy Bit
(SR6). Status Register bit SR6 has two different
functions depending on the current operation.
During Cache Program operations SR6 acts as a
Cache Program Ready/Busy bit, which indicates
whether the Cache Register is ready to accept
new data. When SR6 is set to '0', the Cache Reg-
ister is busy and when SR6 is set to '1', the Cache
Register is ready to accept new data.
During all other operations SR6 acts as a P/E/R Con-
troller bit, which indicates whether the P/E/R Con-
troller is active or inactive. When the P/E/R
Controller bit is set to ‘0’, the P/E/R Controller is
active (device is busy); when the bit is set to ‘1’, the
P/E/R Controller is inactive (device is ready).
P/E/R Controller Bit (SR5). The Program/Erase/
Read Controller bit indicates whether the P/E/R
Controller is active or inactive. When the P/E/R
Controller bit is set to ‘0’, the P/E/R Controller is
active (device is busy); when the bit is set to ‘1’, the
P/E/R Controller is inactive (device is ready).
Cache Program Error Bit (SR1). The Cache Pro-
gram Error bit can be used to identify if the previous
page (page N-1) has been successfully pro-
gramed or not in a Cache Program operation. SR1
is set to ’1’ when the Cache Program operation
has failed to program the previous page (page N-
1) correctly. If SR1 is set to ‘0’ the operation has
completed successfully.
The Cache Program Error bit is only valid during
Cache Program operations, during other opera-
tions it is Don’t Care.
Error Bit (SR0). The Error bit is used to identify if
any errors have been detected by the P/E/R Con-
troller. The Error Bit is set to ’1’ when a program or
erase operation has failed to write the correct data
to the memory. If the Error Bit is set to ‘0’ the oper-
ation has completed successfully. The Error Bit
SR0, in a Cache Program operation, indicates a
failure on Page N.
SR4, SR3 and SR2 are Reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NAND04GW4B2AN1E | 256M X 16 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND02GW4B2AN1T | 128M X 16 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND04GR4B2CN1F | 256M X 16 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND08GW3B2CZL1F | 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52 |
| NAND128W3A2BV6E | 16M X 8 FLASH 3V PROM, 12000 ns, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND08GR3B4CZL6E | 制造商:Micron Technology Inc 功能描述:NAND - Trays |
| NAND08GR3B4CZL6F | 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel |
| NAND08GW3B2AN6E | 功能描述:閃存 4 GBit 2112 Byte 1056 WP 1.8v/3v RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線(xiàn)寬度:1 bit 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類(lèi)型: 接口類(lèi)型:SPI 訪(fǎng)問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| NAND08GW3B2AN6F | 功能描述:閃存 4 GB 2112B 1056 Word Pg 1.8V/3V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線(xiàn)寬度:1 bit 存儲(chǔ)類(lèi)型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類(lèi)型: 接口類(lèi)型:SPI 訪(fǎng)問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| NAND08GW3B2BN6E | 制造商:Micron Technology Inc 功能描述:NAND & S.MEDIA FLASH - Trays |
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