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MVTX2602
Data Sheet
55
Zarlink Semiconductor Inc.
C7RS
Class 7 Reserve Size
516
R/W
0C0
000
QOSC"N"
QOS Control (N=0 - 39)
517- 53E
R/W
0C1-0D2
000
RDRC0
WRED Drop Rate Control 0
553
R/W
0FB
08F
RDRC1
WRED Drop Rate Control 1
554
R/W
0FC
088
USER_
PORT"N"_LOW
User Define Logical Port "N" Low (N=0-7)
580 + 2N
R/W
0D6-0DD
000
USER_
PORT"N"_HIGH
User Define Logical Port "N" High
581 + 2N
R/W
0DE-0E5
000
USER_ PORT1:0_
PRIORITY
User Define Logic Port 1 and 0 Priority
590
R/W
0E6
000
USER_ PORT3:2_
PRIORITY
User Define Logic Port 3 and 2 Priority
591
R/W
0E7
000
USER_ PORT5:4_
PRIORITY
User Define Logic Port 5 and 4 Priority
592
R/W
0E8
000
USER_ PORT7:6_
PRI ORITY
User Define Logic Port 7 and 6 Priority
593
R/W
0E9
000
USER_PORT_
ENABLE
User Define Logic Port Enable
594
R/W
0EA
000
WLPP10
Well known Logic Port Priority for 1 and 0
595
R/W
0EB
000
WLPP32
Well known Logic Port Priority for 3 and 2
596
R/W
0EC
000
WLPP54
Well known Logic Port Priority for 5 and 4
597
R/W
0ED
000
WLPP76
Well-known Logic Port Priority for 7 & 6
598
R/W
0EE
000
WLPE
Well known Logic Port Enable
599
R/W
0EF
000
RLOWL
User Define Range Low Bit7:0
59A
R/W
0F4
000
RLOWH
User Define Range Low Bit 15:8
59B
R/W
0F5
000
RHIGHL
User Define Range High Bit 7:0
59C
R/W
0D3
000
RHIGHH
User Define Range High Bit 15:8
59D
R/W
0D4
000
RPRIORITY
User Define Range Priority
59E
R/W
0D5
000
CPUQOSC1~3
Byte limit for TxQ on CPU port
5A0-5A2
R/W
NA
000
6. MISC Configuration Registers
MII_OP0
MII Register Option 0
600
R/W
0F0
000
MII_OP1
MII Register Option 1
601
R/W
0F1
000
FEN
Feature Registers
602
R/W
0F2
010
MIIC0
MII Command Register 0
603
R/W
N/A
000
MIIC1
MII Command Register 1
604
R/W
N/A
000
MIIC2
MII Command Register 2
605
R/W
N/A
000
Register
Description
CPU Addr
(Hex)
R/W
I2C Addr
(Hex)
Default
Notes