參數(shù)資料
型號: MTVX2602
廠商: Zarlink Semiconductor Inc.
英文描述: Managed 24 Port 10/100 Mbps Ethernet Switch
中文描述: 管理的24端口10/100 Mbps以太網(wǎng)交換機(jī)
文件頁數(shù): 26/147頁
文件大?。?/td> 924K
代理商: MTVX2602
MVTX2602
Data Sheet
26
Zarlink Semiconductor Inc.
Table 3 - PVMAP Register
For example, in the above table, a 1 denotes that an outgoing port is eligible to receive a packet from an incoming
port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port.
In this example:
Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2.
Data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2.
Data packets received at port #2 are
NOT
eligible to be sent to ports 0 and 1.
5.7.2 Tag-Based VLAN
The MVTX2602 supports the IEEE 802.1q specification for “tagging” frames. The specification defines a way to
coordinate VLANs across multiple switches. In the specification, an additional 4-octet header (or “tag”) is inserted in
a frame after the source MAC address and before the frame type. 12 bits of the tag are used to define the VLAN ID.
Packets are then switched through the network with each MVTX2602 simply swapping the incoming tag for an
appropriate forwarding tag rather than processing each packet's contents to determine the path. This approach
minimizes the processing needed once the packet enters the tag-switched network. In addition, coordinating VLAN
IDs across multiple switches enables VLANs to extend to multiple switches.
Up to 255 VLANs are supported in the MVTX2602. The 4 K VLANs specified in the IEEE 802.1q are mapped to 255
VLAN indexes. The mapping is made by the VLAN index mapping table. Based on the VLAN index (VIXn), the
source and destination port membership is checked against the content in the VLAN Index Port association table. If
the destination port is a member of the VLAN, the packet is forwarded; otherwise it is discarded. If the source port is
not a member, a “New VLAN Port” message is sent to the CPU. A filter can be applied to discard the packet if the
source port is not a member of the VLAN.
Destination Port Numbers Bit Map
Port Registers
24
2
1
0
Register for Port #0
PVMAP00_0[7:0] to PVMAP00_3[0]
0
1
1
0
Register for Port #1
PVMAP01_0[7:0] to PVMAP01_3[0]
0
1
0
1
Register for Port #2
PVMAP02_0[7:0] to PVMAP02_3[0]
0
0
0
0
Register for Port #24
PVMAP24_0[7:0] to PVMAP24_3[0]
0
0
0
0
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