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MVTX2602
Data Sheet
43
Zarlink Semiconductor Inc.
10.2 SCAN LINK and SCAN COL interface
An external CPLD logic is required to take the link signals and collision signals from the GPSI PHYs and shift them
into the switch device. The switch device will drive out a signature to indicate the start of the sequence. After that,
the CPLD should shift in the link and collision status of the PHYS as shown in the figure. The extra link status
indicates the polarity of the link signal. One indicates the polarity of the link signal is active high.
Figure 12 - SCAN LINK and SCAN COLLISON Status Diagram
11.0 LED Interface
11.1 LED Interface Introduction
A serial output channel provides port status information from the MVTX2602 chips. It requires three additional pins.
LED_CLK at 12.5 MHz
LED_SYN a sync pulse that defines the boundary between status frames
LED_DATA a continuous serial stream of data for all status LEDs that repeats once every frame time.
A low cost external device (44 pin PAL) is used
to decode the serial data and to drive an LED array for display. This
device can be customized for different needs.
11.2 Port Status
In the MVTX2602, each port has 8 status indicators, each represented by a single bit. The 8 LED status indicators
are:
Bit 0: Flow control
Bit 1:Transmit data
Bit 2: Receive data
Bit 3: Activity (where activity includes either transmission or reception of data)
Bit 4: Link up
Bit 5: Speed (1= 100 Mb/s; 0= 10 Mb/s)
Bit 6: Full-duplex
Bit 7: Collision
Eight clocks are required to cycle through the eight status bits for each port.
25 cycles for link /
24 cycles for col
Drived by CPLD
Total 32 cycles period
Drived by MVTX260x
scan_clk
scan_link/
scan_col