參數(shù)資料
型號: MTVX2602
廠商: Zarlink Semiconductor Inc.
英文描述: Managed 24 Port 10/100 Mbps Ethernet Switch
中文描述: 管理的24端口10/100 Mbps以太網(wǎng)交換機(jī)
文件頁數(shù): 108/147頁
文件大?。?/td> 924K
代理商: MTVX2602
MVTX2602
Data Sheet
108
Zarlink Semiconductor Inc.
13.9.8 OECLK - Internal OE_CLK delay from SCLK
CPU Address: hF07
Accessed by serial interface (RW)
The OE_CLK is used for generating the OE0 and OE1 signals.
PD[15:13] OECLK Delay
000b 80h 8 Buffers Delay
001b 40h 7 Buffers Delay (Recommend)
010b 20h 6 Buffers Delay
011b 10h 5 Buffers Delay
100b 08h 4 Buffers Delay
101b 04h 3 Buffers Delay
110b 02h 2 Buffers Delay
111b 01h 1 Buffers Delay
13.9.9 DA – DA Register
CPU Address: hFFF
Accessed by CPU and serial interface (RO)
Always return 8’h
DA
. Indicate the CPU interface or serial port connection is good.
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