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MVTX2602
Data Sheet
100
Zarlink Semiconductor Inc.
13.7.4 MIIC0 – MII Command Register 0
CPU Address:h603
Accessed by CPU and serial interface only (R/W)
Bit [7:0] - MII Data [7:0]
Note
: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then
program MII command.
13.7.5 MIIC1 – MII Command Register 1
CPU Address:h604
Accessed by CPU and serial interface only (R/W)
Bit [7:0] - MII Data [15:8]
Note
: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
Bit [3]:
Enable VLAN spanning tree support
(Default 0)
0 – Disable
1 – Enable
When VLAN spanning tree is enable the registers ECR1Pn are NOT used to
program the port spanning tree status. The port status is programmed using
the Control Command Frame.
Bit [4]:
Disable IP Multicast Suppor
t (Default 1)
0 – Enable IP Multicast Support
1 – Disable IP Multicast Support
When enable, IGMP packets are identified by search engine and are passed
to the CPU for processing. IP multicast packets are forwarded to the IP
multicast group members according to the VLAN port mapping table.
Bit [5]:
Enable report to CPU
(Default 0)
0 – Disable report to CPU
1 – Enable report to CPU
When disable, new VLAN port association report, new MAC address report
or aging reports are disable for all ports. When enable, register
SE_OPEMODE is used to enable/disable selectively each function.
Bit [6]:
Disable MII Management State Machine
(Default 0)
0: Enable MII Management State Machine
1: Disable MII Management State Machine
Bit [7]:
Disable using MCT Link List structure
(Default 0)
0 – Enable using MCT Link structure
1 - Disable using MCT Link List structure