參數(shù)資料
型號: MT9074AL
廠商: Mitel Networks Corporation
英文描述: T1/E1/J1 Single Chip Transceiver
中文描述: T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁數(shù): 90/122頁
文件大?。?/td> 372K
代理商: MT9074AL
MT9074
Advance Information
90
Bit
Name
Functional Description
7-2
- - -
Unused
1-0
EC9-8
E bit Error Counter.
significant 2 bits of the E bit error
counter.
The most
Table 120 - E-bit Error Counter
(Page 4, Address 14H) (E1)
Bit
Name
Functional Description
7 - 0 EC7-0
E bit Error Counter.
The least
significant 8 bits of the E-bit error
counter.
Table 121 - E-bit Error Counter
(Page 4, Address 15H) (E1)
Bit
Name
Functional Description
7 - 0 BPV15 - 8
Most Significant Bits of the
BPV
significant eight bits of a 16 bit
counter that is incremented once
for every bipolar violation error
received.
Counter.
The
most
Table 122 - Most Significant Bits of the BPV
Counter
(Page 4, Address 16H) (E1)
Bit
Name
Functional Description
7 - 0 BPV7 - 0
Least Significant Bits of the BPV
Counter
. The least significant eight
bits of a 16 bit counter that is
incremented once for every bipolar
violation error received.
Table 123 - Least Significant Bits of the BPV
Counter
(Page 4, Address 17H) (E1)
Bit
Name
Functional Description
7-2
- - -
Unused
1-0
CC9 - 8
CRC-4 Error Counter
These are the
most significant eight bits of the
CRC-64error counter.
Table 124 - CRC-4 Error Counter CEt
(Page 4, Address 18H) (E1)
Bit
Name
Functional Description
7 - 0 CC7 - 0
CRC-4 Error Counter.
These are
the least significant eight bits of the
CRC-4 error counter.
Table 125 - CRC-4 Error Counter CEt
(Page 4, Address 19H) (E1)
Bit
Name
Functional Description
7
TFSYNI
Terminal
Synchronization
When unmasked this interrupt
bit goes high whenever a
change of state of terminal
frame synchronization condition
exists. Reading this register
clears this bit.
Frame
Interrupt
.
6
MFSYNI
Multiframe
Interrupt
. When unmasked this
interrupt bit goes high whenever
a change of state of multiframe
synchronization
exists. Reading this register
clears this bit.
Synchronization
condition
5
CRCSYNI
CRC-4
Interrupt.
When unmasked this
interrupt bit goes high whenever
change of state of CRC-4
synchronization
exists. Reading this register
clears this bit.
Synchronization
condition
4
AISI
Alarm
Interrupt
. When unmasked this
interrupt bit goes high whenever
a change of state of received all
ones condition exists. Reading
this register clears this bit.
Indication
Signal
Table 126 - Interrupt Word Zero
(Page 4, Address 1BH) (E1)
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