參數(shù)資料
型號: MT9074AL
廠商: Mitel Networks Corporation
英文描述: T1/E1/J1 Single Chip Transceiver
中文描述: T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁數(shù): 16/122頁
文件大小: 372K
代理商: MT9074AL
MT9074
Advance Information
16
E1 Digital Interface
PCM 30 (E1) basic frames are 256 bits long and are
transmitted at a frame repetition rate of 8000 Hz,
which results in an aggregate bit rate of 256 bits x
8000/sec = 2.048 Mbits/sec. The actual bit rate is
2.048 Mbits/sec +/-50 ppm encoded in HDB3 format.
The HDB3 control bit (page 01H, address 15H, bit 5)
selects either HDB3 encoding or alternate mark
inversion (AMI) encoding. Basic frames are divided
into 32 time slots numbered 0 to 31, see Figure 34.
Each time slot is 8 bits in length and is transmitted
most significant bit first (numbered bit 1). This results
in a single time slot data rate of 8 bits x 8000/sec. =
64 kbits/sec.
It should be noted that the Mitel ST-BUS also has 32
channels numbered 0 to 31, but the most significant
bit of an eight bit channel is numbered bit 7 (see
Mitel Application Note MSAN-126). Therefore, ST-
BUS bit 7 is synonymous with PCM 30 bit 1; bit 6
with bit 2: and so on (Figure 34).
PCM 30 time slot 0 is reserved for basic frame
alignment, CRC-4 multiframe alignment and the
communication of maintenance information. In most
configurations time slot 16 is reserved for either
Channel Associated Signalling (CAS or ABCD bit
signalling) or Common Channel Signalling (CCS).
The remaining 30 time slots are called channels and
carry either PCM encoded voice signals or digital
data. Channel alignment and bit numbering is
consistent with time slot alignment and bit
numbering. However, channels are numbered 1 to 30
and relate to time slots as per Table 10.
PCM
Timeslots
30
0
1,2,3...15
16
17,18,19,... 31
Voice/Data
Channels
(DSTi/o
and
CSTi/o)
0
1,2,3...15
16
17,18,19,... 31
Table 10 - STBUS vs. PCM-30 to Channel
Relationship(E1)
Frame #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Ft
1
Fs
Notes Frame #
Ft
1
Fs
Notes Frame #
C
o
n
c
e
n
t
r
a
t
o
r
Ft
1
Fs
Notes
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
0
R
e
s
y
n
c
h
r
o
n
i
z
a
t
i
o
n
X
S
S = Spoiler Bits
0
0
0
0
X
S
1
1
1
0
X
C
C = Maintenance Field Bits
0
0
0
1
X
C
1
1
1
1
X
C
0
0
0
1
X
A
A = Alarm Field Bits
1
1
1
0
X
F
i
e
l
d
A
0
0
0
0
X
L
L = Line Switch Field Bits
1
1
1
0
X
L
0
0
0
1
d
a
t
a
X
B
i
t
s
L
1
1
1
1
X
L
0
0
0
1
S
S
S = Spoiler Bits
Table 9 - SLC-96 Framing Structure(T1)
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