參數(shù)資料
型號(hào)： MT9074AL
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁(yè)數(shù)： 13/122頁(yè)
文件大?。?/td> 372K
代理商： MT9074AL
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Advance Information
MT9074
13
Figure 11- TR 62411 Jitter Attenuation Curve
dB
-0.5
0
19.5
J
10
40
400
10K
-20 dB/decade
Frequency (Hz)
Phase Lock Loop (PLL)
The MT9074 contains a PLL, which can be locked to
either an input 4.096 Mhz clock or the extracted line
clock.The PLL will attenuate jitter from less than
2.5 Hz and roll-off at a rate of 20 dB/decade. Its
intrinsic jitter is less than 0.02 UI. The PLL will meet
the jitter transfer characteristics as specified by ATT
document
TR
62411
recommendations as shown in Figure 11.
and
the
relevant
Clock Jitter Attenuation Modes
MT9074 has three basic jitter attenuation modes of
operation, selected by the BS/LS and S/FR control
pins. Referring to the mode names given in Table 5
the basic operation of the jitter attenuation modes
are:
System Bus Synchronous Mode.
Line Synchronous Mode.
Free-run mode.
In System Bus Synchronous mode pins C4b and F0b
are always configured as inputs, while in the Line
Synchronous and Free-Run modes C4b and F0b are
configured as outputs.
In System Bus Synchronous mode an external clock
is applied to C4b. The applied clock is dejittered by
the internal PLL before being used to synchronize
the transmitted data. The clock extracted (with no
jitter attenuation performed) from the receive data
can be monitored on pin E1.5o.
In Line Synchronous mode, the clock extracted from
the receive data is dejittered using the internal PLL
and then output on pin C4b. Pin E1.5o provides the
extracted receive clock before it has been dejittered.
The transmit data is synchronous to the clean
receive clock.
In Free-Run mode the transmit data is synchronized
to the internally generated clock. The internal clock
is output on pin C4b. The clock signal extracted from
the receive data is not dejittered and is output
directly on E1.5o.
Depending on the mode selection above, the PLL
can either attenuate transmit clock jitter or the
receive clock jitter. Table 5 shows the appropriate
configuration of each control pin to achieve the
Mode Name
BS/LS
S/FR
Note
System Bus
Synchronous
1
1
PLL locked to C4b.
Line Synchronous
0
1
PLL locked to E1.5o.
Free-Run
x
0
PLL free - running.
Table 5 - Selection of clock jitter attenuation
modes using the M/S and MS/FR pins
相關(guān)PDF資料
PDF描述
MT9074AP T1/E1/J1 Single Chip Transceiver
MT9074 T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
MT9075 E1 Single Chip Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9074AL1 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays
MT9074AP 制造商:Microsemi Corporation 功能描述:
MT9074AP1 制造商:Microsemi Corporation 功能描述:T1/E1/J1 SGLE CHIP XSCR 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TXRX SGL T1/E1 68PLCC 制造商:Microsemi Corporation 功能描述:IC TXRX SGL T1/E1 68PLCC
MT9074APR 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver
MT9074APR1 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Tape and Reel
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