參數資料
型號： MT90220
廠商： Mitel Networks Corporation
英文描述： Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設備（八端口ATM IMA和UNI處理器）)
中文描述： 八路IMA的/單向物理層設備（八端口IMA的/單向物理層設備（八端口自動柜員機IMA的和單向處理器））
文件頁數： 58/118頁
文件大小： 310K
代理商： MT90220
MT90220
50
7.3
TX ICP Register Description
Tables 38 to 40 describe the
TX ICP
registers.
Address (Hex):
Direct access
Reset Value (Hex):
148
Controls the transfer of TX ICP cells and frame pulse indication
0F
Bit #
Type
Description
7
6
5
4
3
R/W
R/W
R/W
R/W
R/W
When 1 indicates the end of a frame was detected in IMA Group #3. Cleared by writing 0.
When 1 indicates the end of a frame was detected in IMA Group #2. Cleared by writing 0.
When 1 indicates the end of a frame was detected in IMA Group #1. Cleared by writing 0.
When 1 indicates the end of a frame was detected in IMA Group #0. Cleared by writing 0.
When 1 indicate that the transfer of the TX ICP cell for IMA Group #3 is complete. Write 0
to initiate a transfer.
When 1 indicate that the transfer of the TX ICP cell for IMA Group #2 is complete. Write 0
to initiate a transfer.
When 1 indicate that the transfer of the TX ICP cell for IMA Group #1 is complete. Write 0
to initiate a transfer.
When 1 indicate that the transfer of the TX ICP cell for IMA Group #0 is complete. Write 0
to initiate a transfer.
2
R/W
1
R/W
0
R/W
Table 38 - TX ICP Cell Handler Register
Address (Hex):
Direct access
Reset Value (Hex):
149
Interrupt Enable register for the TX ICP Handler register
00
Bit #
Type
Description
7
R/W
Write a 1 will enable the generation of an interrupt from the end of a frame detection for
IMA Group 3. A 0 will inhibit the generation of an interrupt.
Write a 1 will enable the generation of an interrupt from the end of a frame detection for
IMA Group 2. A 0 will inhibit the generation of an interrupt.
Write a 1 will enable the generation of an interrupt from the end of a frame detection for
IMA Group 1. A 0 will inhibit the generation of an interrupt.
Write a 1 will enable the generation of an interrupt from the end of a frame detection for
IMA Group 0. A 0 will inhibit the generation of an interrupt.
Write a 1 will enable the generation of an interrupt when the transfer of the TX ICP cell for
the IMA Group 3 is completed. A 0 will inhibit the generation of an interrupt.
Write a 1 will enable the generation of an interrupt when the transfer of the TX ICP cell for
the IMA Group 2 is completed. A 0 will inhibit the generation of an interrupt.
Write a 1 will enable the generation of an interrupt when the transfer of the TX ICP cell for
the IMA Group 1 is completed. A 0 will inhibit the generation of an interrupt.
Write a 1 will enable the generation of an interrupt when the transfer of the TX ICP cell for
the IMA Group 0 is completed. A 0 will inhibit the generation of an interrupt.
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Table 39 - TX ICP Cell Interrupt Enable Register
相關PDF資料
PDF描述
MT90221 Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設備（四端口ATM IMA和UNI處理器）)
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相關代理商/技術參數
參數描述
MT90220AL 制造商:Zarlink Semiconductor Inc 功能描述:I.C.
MT90220ALX01 制造商:Mitel Networks Corporation 功能描述:
MT90221 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
MT90221AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
MT90222 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device
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