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參數(shù)資料
| 型號： | MT90220 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設(shè)備（八端口ATM IMA和UNI處理器）) |
| 中文描述： | 八路IMA的/單向物理層設(shè)備（八端口IMA的/單向物理層設(shè)備（八端口自動柜員機(jī)IMA的和單向處理器）） |
| 文件頁數(shù)： | 52/118頁 |
| 文件大?。?/td> | 310K |
| 代理商： | MT90220 |
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MT90220
44
Address (Hex):
Direct access
205
1 register to enable interrupts from IMA Groups. The RxClk signal must be
active for correct register operation
00
Reset Value (Hex):
Bit #
Type
Description
7-4
3
R
Unused. Read all 0’s.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 3.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 2.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 1.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Group 0.
R/W
2
R/W
1
R/W
0
R/W
Table 21 - RX UTOPIA IMA Group FIFO Overflow Enable Register
Address (Hex):
Direct access
221
1 register to enable interrupts from the links in UNI mode. The RxClk signal must
be active for correct register operation
00
Reset Value (Hex):
Bit #
Type
Description
7
R/W
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link7.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 6.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 5.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 4.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link3.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 2.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 1.
When set to 1, the corresponding bit in the IRQ UTOPIA UNI Overflow Status register can
generate an interrupt. A value of 0 inhibits the generation of an interrupt. Link 0.
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Table 22 - RX UTOPIA Link FIFO Overflow Enable Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90221 | Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備（四端口ATM IMA和UNI處理器）) |
| MT90401 | SONET/SDH System Synchronizer(SONET/SDH 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
| MT9040 | T1/E1 Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
| MT9041A | () |
| MT9041B | T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90220AL | 制造商:Zarlink Semiconductor Inc 功能描述:I.C. |
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
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