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參數(shù)資料
| 型號(hào)： | MT90220 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設(shè)備（八端口ATM IMA和UNI處理器）) |
| 中文描述： | 八路IMA的/單向物理層設(shè)備（八端口IMA的/單向物理層設(shè)備（八端口自動(dòng)柜員機(jī)IMA的和單向處理器）） |
| 文件頁(yè)數(shù)： | 45/118頁(yè) |
| 文件大?。?/td> | 310K |
| 代理商： | MT90220 |
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MT90220
37
The indirect method is identified with ’S’ (indirect and
need to synchronize with a ready bit) whereas the
direct access is identified with a ’D’ in the register
tables.
6.3.2
Direct access registers can be written or read
directly by the microprocessor, without having to use
otherregisters. Upon a write access to the MT90220
internal registers, the data is stored in an internal
latch and transferred to the destination register
within 2.5 system clock cycles (100 nsec at 25 MHz).
No specific action is required if the microprocessor
provides at least 100 nsec (with Chip Select signal
inactive) between 2 consecutive write accesses or
between a write and a read back of the same
register. If the microprocessor is faster, then
consecutive accesses must be inhibited or wait
state(s) introduced (this option is available on most
MCUs).
Direct Access
6.3.3
Indirect access registers cannot be accessed directly
by the microprocessor. The value is transferred back
and forth using registers which hold a copy of the
information (data) and internal address of the
register. This is required to stabilize the read value.
Consider for example the transfer of a TX ICP cell
that requires almost 200 system clock cycles. A
dedicated ready bit which can optionally generate an
interrupt is implemented for this type of transfer.
Accessing any of the 24 bit counters provides
another example. A ready bit is implemented in the
Counter Transfer Command register when the
transfer is completed.
Indirect Access
When accessing indirect registers specified by the
RX Delay Select
or
RX Load Values/Link Select
registers, the value in the indirect registers can be
read when the write to the selection register is
effectively done (i.e. 2.5 system clock cycles after
the write cycle is completed). There is no additional
delay required.
6.3.4
The status bits will remain set until cleared by a
specific write action from the microprocessor. Status
bits are cleared by overwriting a zero to the
corresponding position in the source register. Each
input status register has a related interrupt enable
register. When enabled, setting a bit in the interrupt
enable register causes an interrupt to occur in the
corresponding status register bit.
Clearing of Status Bits
6.3.4.1
Some registers include a toggle bit. Toggle bits are
used to indicate a write action to any internal register
has taken place. Typically, this bit is toggled 2.5
system clock cycles after performing the write action.
To use the toggle bit, its state (either 0 or 1) must be
read (polled) and its state is changed (toggled) when
a write command is completed. This bit is particularly
useful when the processor clock is much faster than
the MT90220 system clock.
Toggle Bit
6.3.5
Access is provided to the External SRAM from the
microprocessor using a special test mode and test
registers (i.e., to assist in debugging or verification).
The test mode is enabled by writing to bit 7 of the
Test Mode Enable
register, writing 0x10 to the
RX
Delay Link Number
register and by writing 0x29 to
the
RX External SRAM Control
register. Indirect
access is provided using the
RX External SRAM
Read/Write Data
register for the data to be written or
read and the
RX SRAM External Address 0
,
1
and
2
registers for the address of the SRAM location. The
write transfer command is issued using the
RX
External SRAM Control
register. Bit 7 of the
RX
External SRAM Control
is cleared (set to 0) and
then returned to 1 when the write action is
completed.
Test Modes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90221 | Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備（四端口ATM IMA和UNI處理器）) |
| MT90401 | SONET/SDH System Synchronizer(SONET/SDH 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）) |
| MT9040 | T1/E1 Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）) |
| MT9041A | () |
| MT9041B | T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90220AL | 制造商:Zarlink Semiconductor Inc 功能描述:I.C. |
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
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