參數(shù)資料
型號(hào)： MT90220
廠商： Mitel Networks Corporation
英文描述： Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設(shè)備（八端口ATM IMA和UNI處理器）)
中文描述： 八路IMA的/單向物理層設(shè)備（八端口IMA的/單向物理層設(shè)備（八端口自動(dòng)柜員機(jī)IMA的和單向處理器））
文件頁(yè)數(shù)： 36/118頁(yè)
文件大?。?/td> 310K
代理商： MT90220
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MT90220
28
the interface clocks (RXCK and TXCK) operate
at 2.048 MHz only
the synchronization signals (TXSYNC and
RXSYNC) are valid for one clock cycle (488
nsec) during the first bit of the frame
In PCM Mode 3, the TXCK and TXSYNC pins
are defined as outputs.
In PCM Mode 7, the TXCK and TXSYNC are
defined as inputs.
The edge of the RXCK and TXCK signals that is
used to sample the incoming, and transmit the
outgoing, data is fully programmable on a per link
basis. This allows the MT90220 to operate with the
majority of off-the-shelf E1 framers.
The MT90220 does not use timeslots 0 and 16 to
perform the G.804 transmission convergence
function (see Figure 13).
4.2.5
TXSYNC Signal in Mode 5 and 7
The TXSYNC signal is defined as an input in PCM
mode 5 and 7 and is sampled at the bit boundary. A
positive delay of 10 nsec is expected between the
TXCLK signal at the bit boundary and the time the
TXSYNC changes. This may cause some inter-
operability
problems
when
connected to some off-the-shelf framers as the
TXSYNC can be slightly ahead of the TXCLK signal.
In this case, the TXSYNC signal need to be delayed
to ensure proper operation of the TX PCM port.
the
MT90220
is
4.3
In PCM Modes 2, 4, 5 and 7, the TXCK and TXSYNC
are inputs and are generated by external circuitry.
In PCM Modes 1, 3, 6 and 8, the TXCK and TXSYNC
are outputs. TXCK source is software selectable and
Clocking Options
can be any of the eight RXCK signals or four external
REFCK inputs (see Figure 14). The TXSYNC is
generated from the TXCK signal.
The RXCK pins are always defined as inputs and the
proper signal must be provided to each input.
4.3.1
The RXSYNC signal is used to align the incoming
DSTi data to retrieve all the T1 or E1 channels. The
RXSYNC pulse can be present for each PCM frame
(8Khz) or once per Superframe (every 12 or 24 PCM
frames). The period and position of the RXSYNC is
verified for each receive block independently. A status
bit (1 per link) in the
RX Sync Status
register is set if
the synchronization pulse occurs at an unexpected
time in the frame. The RX block will be re-aligned with
this new synchronization pulse.
Verification of the RXSYNC Period
4.3.2
The TXSYNC signal is used to align the outgoing
DSTo data to retrieve all the T1 or E1 channels.
When defined as input, the TXSYNC pulse can be
present for each PCM frame (8Khz) or once per
Superframe (every 12 or 24 PCM frames). The
period and position of the TXSYNC is verified for
each transmit block independently. A status bit (1 per
link) in the
TX Sync Status
register is set if the
synchronization pulse occurs at an unexpected time
in the frame. The TX block will be re-aligned with this
new synchronization pulse.
Verification of the TXSYNC Period
4.3.3
Two output pins are provided to simplify the external
circuitry required when using an external PLL. These
two pins, PLLREF0 and PLLREF1, re-route any of
the eight RXCK signals and drive the primary and
secondary reference signals of a PLL under software
Primary and Secondary Reference Signals
Figure 12 - Mode 1 and 5: Generic PCM Interface for T1
T1 Frame
Bit Cells
at DSTx0-7
bit 193
bit 1
bit 2
...
Serial Bit
Stream
Bit Cell
...
Bit Cell
TXSYNC
RXSYNC
TXCK
RXCK
...
...
...
Unused or
High Impedance
相關(guān)PDF資料
PDF描述
MT90221 Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備（四端口ATM IMA和UNI處理器）)
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MT9041A ()
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90220AL 制造商:Zarlink Semiconductor Inc 功能描述:I.C.
MT90220ALX01 制造商:Mitel Networks Corporation 功能描述:
MT90221 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
MT90221AL 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
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