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參數(shù)資料
| 型號： | MT90220 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設備（八端口ATM IMA和UNI處理器）) |
| 中文描述： | 八路IMA的/單向物理層設備（八端口IMA的/單向物理層設備（八端口自動柜員機IMA的和單向處理器）） |
| 文件頁數(shù)： | 35/118頁 |
| 文件大小： | 310K |
| 代理商： | MT90220 |
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MT90220
27
Figure 11 - PCM Mode 4 and 8: ST-BUS Interface for E1
Table 10 - Channel Mapping from ST-BUS to E1
E1 Time-Slots
Voice/Data Channels
(DSTi/o)
E1 Time-Slots
Voice/Data Channels
(DSTi/o)
-
0
x
-
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
16
x
Serial Bit
Stream
Bit Cell
Bit Cell
...
...
High Impedance
High Impedance
Unused or
ST-BUS
Bit Cells
(DSTx0-7)
Channel 31 bit 0
Channel 0 bit 7
TXSYNC
RXSYNC
TXCK
RXCK
Channel 0 bit 0
Channel 1 bit 7
...
...
...
...
...
...
ST-BUS
Bit Cells
(DSTx0-7)
Channel 15 bit 0
Channel 16 bit 7
Serial Bit
Stream
Bit Cell
TXSYNC
RXSYNC
TXCK
RXCK
Channel 16 bit 0
Channel 17 bit 7
Bit Cell
...
...
...
...
...
...
...
...
Unused or
Unused or
High Impedance
Unused or
High Impedance
1, the TXCK and TXSYNC pins are outputs. In the
PCM Mode 5, the TXCK and TXSYNC pins are
defined as inputs.
4.2.3.1
1.544 MHz Clock
In this sub-mode, (selected by clearing the bit 4 of
the TX PCM Control Register 1,) the serial PCM
Interface rate is equal to the line bit rate. When
selected to operate in this sub-mode, the interface
clock is 1.544 MHz and the DSTo and DSTi the data
lines transport only 24 time-slots plus the DS1
framing bit for a total of 193 bits per frame.
The frequency value for TXSYNC and RXSYNC is 8
kHz. The frequency for the TXCK and RXCK is 1.544
Mhz.
The edge of the RXCK and TXCK signals used to
sample incoming data and transmit the outgoing data
is fully programmable on a per link basis. This allows
the MT90220 to operate with the majority of available
off-the-shelf T1 framers.
When operating in the generic PCM system Interface
at 1.544 MHz, the MT90220 does not use the first bit
of the PCM frame (i.e., the T1 framing bit) to perform
the G.804 recommended transmission convergence
function (see Figure 12). This frame bit is also
ignored on the receive side. The position of the
frame bit is indicated by the TXSYNC and RXSYNC
signals.
4.2.3.2
In this sub-mode (selected by setting the bit 4 of the
TX PCM Control Register 1) the channel/timeslot
mapping for this mode is similar to the ST-BUS mode
for T1. The same PCM mapping schemes (grouped
or spaced) are supported. The TXCLK and RXCLK
are 2.048 MHz signal and the TXSYNC and
RXSYNC are a frame pulse of one full bit duration
that occurs at the beginning of the frame. The frame
rate is 8 KHz. The polarity of the TXCK, RXCK,
TXSYNC and RXSYNC and their active edge is
programmable using
TX PCM Link Control
register
number 1 and
RX PCM Link Control
register.
2.048 MHz Clock
4.2.4
The channel/timeslot mapping in this mode is similar
to the ST-BUS mode for E1. The differences are:
Mode 3 and 7: Generic PCM Interface for E1
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|---|---|
| MT90221 | Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設備（四端口ATM IMA和UNI處理器）) |
| MT90401 | SONET/SDH System Synchronizer(SONET/SDH 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
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| MT9041A | () |
| MT9041B | T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90220AL | 制造商:Zarlink Semiconductor Inc 功能描述:I.C. |
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
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