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參數(shù)資料
| 型號： | MT90220 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設備（八端口ATM IMA和UNI處理器）) |
| 中文描述： | 八路IMA的/單向物理層設備（八端口IMA的/單向物理層設備（八端口自動柜員機IMA的和單向處理器）） |
| 文件頁數(shù)： | 23/118頁 |
| 文件大?。?/td> | 310K |
| 代理商： | MT90220 |
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MT90220
15
reported in the
TX IMA Mode Status register
. It
then can be assigned to another IMA group.
When removing the last link of a TX IMA group, the
TX Utopia FIFO
has to be empty. This can easily be
done by first disabling the source of ATM cells (ATM
Utopia contoller), then disabling the
TX Utopia Port
using the UTOPIA input Link or Group PHY enable
registers while still keeping the "Send User Cell" bit
of the TX Link Control Centre register set to 1. The
level of the
TX Utopia FIFO
can be monitored using
TX Utopia FIFO Level register
. The above
procedure can then be applied to assign the link in
UNI mode.
When the link is configured in UNI mode, IDLE cells
are transmitted. Writing to the
TX PCM Link Control
registers either turns off the transmitter or
reconfigures the link into another mode.
2.5
A maximum of eight independent T1/E1 interfaces
can be selected in UNI mode. Figure 4 gives a
functional block diagram of the transmitter in UNI
mode.
ATM Transmit Path in UNI Mode
ATM cells received from the ATM port are placed in a
TX UTOPIA FIFO, waiting to be transmitted. If the
Idle/Unassigned cell removal option is selected,
these cells are dropped. If the TX UTOPIA FIFO is
empty, an Idle cell is sent to the output link. The
content of the Idle cell is pre-initialized with the
header bytes set at 0x00, 0x00, 0x00 and 0x01. The
payload bytes are set to 0x6A.
TX UTOPIA FIFO Length Definition
registers are
used to set the TX UTOPIA FIFO size. The total
number of cells in all the TX UTOPIA FIFOs and TX
Link FIFO (includes the links used in IMA Mode and
the links used in UNI Mode) is limited to 58.
Idle Cells are transmitted on the UNI PCM Interface
until the bit corresponding to the link in the
UTOPIA
Input Link PHY Enable
register is set. Then, the
ATM User cells are transferred from the Input
UTOPIA port to the TX PCM port.
3.0 The ATM Receive Path
The receive path corresponds to the cell flow from
the T1/E1 interfaces to the ATM UTOPIA Interface.
The MT90220 provides cell delineation and optional
cell filtering to discard Unassigned or Idle cells on
each link. The incoming cells are stored in the
external RAM required in IMA mode to perform cell
recovery due to delay variation between the links
introduced by the network.
3.1
This block provides the circuitry necessary to
perform functions such as Cell Delineation (CD), cell
payload de-scrambling, HEC verification and filtering
of Idle (UNI) cells. The CD circuit delineates ATM
cells received from the payload of the T1 or E1 frame
through the PCM Interface.
Cell Delineation Function
When
calculations
boundaries. The CD circuit performs a sequential
byte by byte hunt for a correct HEC sequence. While
performing this hunt, the cell delineation state
machine is in the HUNT state. Figure 5 depicts a
state diagram of the cell delineation operation.
performing
are
delineation,
interpreted
correct
indicate
HEC
cell
to
Figure 5 - Cell Delineation State Diagram
When a correct HEC is found, the CD circuit locks on
the cell boundary and enters the PRESYNC state.
The PRESYNC state keeps checking the HEC to
ensure that the previous indication was not false.
HUNT
Correct HEC (byte by byte)
PRESYNC
SYNC
ALPHA
Consecutive
Incorrect HEC
(cell by cell)
DELTA Consecutive
Correct HEC
(cell by cell)
Incorrect HEC
(cell by cell)
Figure 6 - SYNC State Block Diagram
Correction
Cell
Accepted
Detection
Cell
Discarded
HCS Single Bit Error Detected (corrected or dropped)
HCS Multi-Bit Error Detected (cell discarded)
No HCS Errors Detected
DELTA
Consecutive
Correct HCS’s
(PRESYNC State)
ALPHA
Consecutive
Incorrect HCS’s
Jump to HUNT
State
ATM CELL DELINEATION SYNC STATE
相關PDF資料 |
PDF描述 |
|---|---|
| MT90221 | Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設備（四端口ATM IMA和UNI處理器）) |
| MT90401 | SONET/SDH System Synchronizer(SONET/SDH 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
| MT9040 | T1/E1 Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
| MT9041A | () |
| MT9041B | T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90220AL | 制造商:Zarlink Semiconductor Inc 功能描述:I.C. |
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
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