參數(shù)資料
型號(hào)： MT90220
廠(chǎng)商： Mitel Networks Corporation
英文描述： Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設(shè)備（八端口ATM IMA和UNI處理器）)
中文描述： 八路IMA的/單向物理層設(shè)備（八端口IMA的/單向物理層設(shè)備（八端口自動(dòng)柜員機(jī)IMA的和單向處理器））
文件頁(yè)數(shù)： 24/118頁(yè)
文件大?。?/td> 310K
代理商： MT90220
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MT90220
16
False indications are interpreted to mean the circuit
is not tracking good ATM cells. After entering the
PRESYNC state, the first false indication triggers a
transition back to HUNT state.
If the PRESYNC state HEC is correct, then a
transition to the SYNC state occurs after “
δ
” cells
(DELTA in ITU I.432) are correctly received. In the
SYNC state, the CD circuit treats the incoming ATM
cell stream as stable and the MT90220 functions
normally.
While in the SYNC state, if an incorrect HEC is
obtained “a” consecutive times (ALPHA in ITU I.432),
cell delineation is considered lost and a transition is
made back to the HUNT state (see Figure 6).
As defined by the ITU I.432 recommendations, the
value of ALPHA and DELTA determine the
robustness of the delineation method. The value of
ALPHA and DELTA for the Cell Delineation state
machine are defined in the
Cell Delineation
register.
Only one set of values is defined for the eight Cell
Delineation state machines. The status of the CD
state machine for each link is available in bits 0 and 1
of the
RX Cell Delineation State
register.
The ITU I.432 suggested values are: ALPHA = 7;
and DELTA = 6.
Loss of Cell Delineation (LCD) is detected by
counting the number of incorrect cells while in HUNT
state. The MT90220 provides an internal
Loss Cell
Delineation
register to set the threshold for this
count. A value of 360 in the LCD register would
correspond to 79 msec for E1 and 100 msec for T1
applications. The LCD state for each link is available
in bit 1 of the
IRQ LinkStatus
registers, and in bit 6
of the
RX Link ID Number
register.
The LCD status bit is reporting the current condition
of the Cell Delineation State Machine at the time it is
read and cannot not be programmed to generate an
interrupt when exiting the LCD condition. The
software has to poll the status bit to determine when
the condition is cleared.
Table 3 provides the time, in microseconds, for the
CD circuit to receive a full ATM cell from the T1 and
E1 frame payloads.
Table 3 - Cell Acquisition Time
While the cell delineation state machine is in the
SYNC state, the verification circuit implements the
state machine shown in Figure 6.
In normal operation, the HEC verification state
machine remains in the ’correction’ state. Incoming
cells containing no HEC errors are passed to the
receive IMA block (RX IMA). Incoming single-bit
errors can be corrected if required by the application
(i.e., single bit error correction can be enabled or
disabled).
After correction (when enabled), the resulting ATM
cell is passed to the RX IMA block for IMA
sequencing control.
If a single or multi bit error occurs, the state machine
goes to the ’detection’ state. When a cell with a good
HEC is detected, the state machine returns to the
’correction’ state. The HEC calculation normally
includes the ATM FORUM polynomial (X
6
+ X
4
+ X
2
+ 1). The use of the polynomial can be disabled by
writing to bit 1 of the
RX Link Control
register.
3.2
The CD circuit can de-scramble the cell payload
field. The de-scrambling algorithm can be enabled or
disabled using bit 5 of the
RX Link Control
registers.
De-Scrambling and ATM Cell Filtering
The MT90220 can be programmed, using the
RX
Link Control
registers, to discard received ATM cells
with HEC error.
HEC error correction is optional and can be enabled
by the CPU. When the option to correct an incoming
HEC value with 1 bit error is selected, the HEC is
corrected and the cell is not counted as a cell with a
bad HEC. If the option to remove the cells that are
received with a bad HEC is selected, then the
incoming cells are replaced by a Filler cell in IMA
mode. The cell is simply discarded when in UNI
mode. The counter is not incremented if the HEC
value is corrected, when the option is enabled.
Incoming Idle and Unassigned cells can be detected
and dropped automatically.
3.3
The block diagram at Figure 7 illustrates the
MT90220 IMA mode receive path. The receiver must
rearrange the incoming bit streams from N-links (1
≤
N
≤
8) into a single UTOPIA cell stream.
ATM Receive Path in IMA Mode
Format
Average Cell Acquisition Time (
μ
s)
T1
E1
276
221
相關(guān)PDF資料
PDF描述
MT90221 Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備（四端口ATM IMA和UNI處理器）)
MT90401 SONET/SDH System Synchronizer(SONET/SDH 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）)
MT9040 T1/E1 Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）)
MT9041A ()
MT9041B T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90220AL 制造商:Zarlink Semiconductor Inc 功能描述:I.C.
MT90220ALX01 制造商:Mitel Networks Corporation 功能描述:
MT90221 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
MT90221AL 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
MT90222 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device
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