- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385640 > MT58L512Y32D (Micron Technology, Inc.) 16Mb SYNCBURST⑩ SRAM PDF資料下載
參數(shù)資料
| 型號： | MT58L512Y32D |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 16Mb SYNCBURST⑩ SRAM |
| 中文描述： | ⑩的SRAM 16Mb的SYNCBURST |
| 文件頁數(shù)： | 3/34頁 |
| 文件大?。?/td> | 526K |
| 代理商： | MT58L512Y32D |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
3
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
GENERAL DESCRIPTION (continued)
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can be
from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be in-
ternally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During WRITE cycles on the x18 device,
BWa# controls DQas and DQPa; BWb# controls DQbs
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQas and DQPa; BWb# controls
DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
NOTE:
1. No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x18
NC
NC
NC
x32/x36
NC/
DQPc
1
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32/x36
NC/
DQPa
1
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
ZZ
V
DD
NC
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
NC
NC
DQa
DQa
DQa
DQa
DQPa
NC
V
SS
V
DD
Q
NC
NC
NC
DQd
DQd
NC/
DQPd
1
MODE (LBO#)
SA
SA
SA
SA
SA1
SA0
DNU
DNU
V
SS
V
DD
SA
SA
SA
SA
SA
SA
SA
SA
SA
controls DQds and DQPd. GW# LOW causes all bytes to
be written. Parity bits are only available on the x18 and
x36 versions.
This device incorporates an additional pipelined
enable register which delays turning off the output
buffer an additional cycle when a deselect is executed.
This feature allows depth expansion without penalizing
system performance.
Micron’s 16Mb SyncBurst SRAMs operate from a
+3.3V or +2.5V power supply, and all inputs and outputs
are TTL-compatible. Users can implement either a 3.3V
or 2.5V I/O for the +3.3V V
DD
or a 2.5V I/O for the +2.5V
V
DD
. The device is ideally suited for Pentium
and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
Please to (www.micronsemi.com/en/products/sram/
) for the lat-
Micron siteV
SS
V
DD
Q
NC
NC
SA
DQb
DQb
NC/
DQPb
1
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
BWc#
BWd#
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT58L64L18F | 64K x 18, 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態(tài)RAM) |
| MT58L32L32F | 32K x 32， 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態(tài)RAM) |
| MT58L32L36F | 32K x 36， 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出，流通式同步脈沖靜態(tài)RAM) |
| MT58L64L18P | 64K x 18, 3.3V I/O, Pipelined, SCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L32L32P | 32K x 32, 3.3V I/O, Pipelined, SCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L512Y32DT-10 | 制造商:Cypress Semiconductor 功能描述:512KX32 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512Y32DT-10 ES | 制造商:Cypress Semiconductor 功能描述:512KX32 SRAM PLASTIC TQFP 3.3V |
| MT58L512Y32DT-6 | 制造商:Cypress Semiconductor 功能描述:DS2KX32 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512Y32PT-10 IT | 制造商:Cypress Semiconductor 功能描述:16MB 512KX32 SRAM PLASTIC IND |
| MT58L512Y32PT-6 | 制造商:Cypress Semiconductor 功能描述:512KX32 SRAM PLASTIC TQFP 3.3V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。