參數(shù)資料
型號: MT58L512Y32D
廠商: Micron Technology, Inc.
英文描述: 16Mb SYNCBURST⑩ SRAM
中文描述: ⑩的SRAM 16Mb的SYNCBURST
文件頁數(shù): 20/34頁
文件大?。?/td> 526K
代理商: MT58L512Y32D
20
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
READ TIMING
3
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
GW#, BWE#,
BWa#-BWd#
Q
High-Z
tKQLZ
tKQX
tKQ
ADV#
tOEHZ
tKQ
Single READ
BURST READ
tOEQ
tOELZ
tKQHZ
Burst wraps around
to its initial state.
tAAH
tAAS
tWH
tWS
tADSH
tADSS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A2 + 3)
A2
A3
(NOTE 1)
Deselect
cycle.
(NOTE 3)
Burst continued with
new base address.
(NOTE 4)
ADV# suspends burst.
DON’T CARE
UNDEFINED
NOTE:
1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q
to be driven until after the following clock rising edge.
4. Outputs are disabled within two clock cycles after deselect.
-6
-7.5
-10
SYM
t
AS
t
ADSS
t
AAS
t
WS
t
CES
t
AH
t
ADSH
t
AAH
t
WH
t
CEH
MIN
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ TIMING PARAMETERS
-6
-7.5
-10
SYM
t
KC
f
KF
t
KH
t
KL
t
KQ
t
KQX
t
KQLZ
t
KQHZ
t
OEQ
t
OELZ
t
OEHZ
MIN
6.0
MAX
MIN
7.5
MAX
MIN
10
MAX
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
166
133
100
2.3
2.3
2.5
2.5
3.0
3.0
3.5
4.0
5.0
1.5
0
1.5
0
1.5
1.0
3.5
3.5
4.2
4.2
5.0
5.0
0
0
0
3.5
4.2
4.5
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