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參數(shù)資料
| 型號： | MT55L64L32F1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 64K x 32,3.3V I/O, ZBT SRAM(2Mb,3.3V輸入/輸出，靜態(tài)RAM) |
| 中文描述： | 64K的x 32,3.3六/ O的ZBT SRAM的（處理器，3.3V的輸入/輸出，靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 9/23頁 |
| 文件大小： | 406K |
| 代理商： | MT55L64L32F1 |
9
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM
MT55L128L18F1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, FLOW-THROUGH ZBT SRAM
FBGA PIN DESCRIPTIONS (continued)
x18
8B
x32/x36
8B
SYMBOL
OE#(G#)
TYPE
Input
DESCRIPTION
Output Enable: This
active LOW, asynchronous input enables the
data I/O output drivers.
Synchronous Address Advance/Load: When HIGH, this input is
used to advance the internal burst counter, controlling burst
access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ingored. A LOW on ADV/LD# clocks a new
address at the CLK rising edge.
Mode: This input selects the burst sequence. A LOW on this
input selects
“
linear burst.
”
NC or HIGH on this input selects
“
interleaved burst.
”
Do not alter input state while device is
operating.
SRAM Data I/Os: For the x18 version, Byte
“
a
”
is associated DQas;
Output Byte
“
b
”
is associated with DQbs. For the x32 and x36 versions,
Byte
“
a
”
is associated with DQas; Byte
“
b
”
is associated with DQbs;
Byte
“
c
”
is associated with DQcs; Byte
“
d
”
is associated with DQds.
Input data must meet setup and hold times around the rising edge
of CLK.
8A
8A
ADV/LD#
Input
1R
1R
MODE
(LB0#)
Input
(a)
10J, 10K,
10L, 10M, 11D, 10L, 10M, 11J,
11E, 11F, 11G 11K, 11L, 11M
(b)
1J, 1K,
1L, 1M, 2D,
2E, 2F, 2G
(a)
10J, 10K,
DQa
Input/
(b)
10D, 10E,
10F, 10G, 11D,
11E, 11F, 11G
(c)
1D, 1E,
1F, 1G, 2D,
2E, 2F, 2G
(d)
1J, 1K, 1L,
1M, 2J, 2K,
2L, 2M
11N
11C
1C
1N
DQb
DQc
DQd
11C
1N
–
–
NC/
DQPa
NC/
DQPb
NC/
DQPc
NC/
DQPd
V
DD
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these are No
Connect (NC). On the x18 version, Byte
“
a
”
parity is DQPa; Byte
“
b
”
parity is DQPb. On the x36 version, Byte
“
a
”
parity is DQPa; Byte
“
b
”
parity is DQPb; Byte
“
c
”
parity is DQPc; Byte
“
d
”
parity is DQPd.
Supply Power Supply:
See DC Electrical Characteristics and Operating
Conditions for range.
2H, 4D, 4E, 4F, 2H, 4D, 4E, 4F,
4G, 4H, 4J,
4K, 4L, 4M,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
4G, 4H, 4J,
4K, 4L, 4M,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
V
DD
Q
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
(continued on next page)
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| MT55L64L32F1T-10 | 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V |
| MT55L64L32F1T-12 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 2M-Bit 64K x 32 9ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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