- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385640 > MT55L64L32F1 (Micron Technology, Inc.) 64K x 32,3.3V I/O, ZBT SRAM(2Mb,3.3V輸入/輸出，靜態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | MT55L64L32F1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 64K x 32,3.3V I/O, ZBT SRAM(2Mb,3.3V輸入/輸出，靜態(tài)RAM) |
| 中文描述： | 64K的x 32,3.3六/ O的ZBT SRAM的（處理器，3.3V的輸入/輸出，靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 406K |
| 代理商： | MT55L64L32F1 |
16
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM
MT55L128L18F1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, FLOW-THROUGH ZBT SRAM
NOTE:
1. Measured as HIGH above V
IH
and LOW below V
IL
.
2. Refer to Technical Note TN-55-01,
“
Designing with ZBT SRAMs,
”
for a more thorough discussion on these parameters.
3. This parameter is sampled.
4. Output loading is specified with C
= 5pF as shown in Figure 2.
5. Transition is measured ±200mV from steady state voltage.
6. OE# can be considered a
“
Don
’
t Care
”
during WRITEs; however, controlling OE# can help fine-tune a system for
turnaround timing.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times
with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK when ADV/LD# is LOW to remain enabled.
8. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.
9. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
AC ELECTRICAL CHARACTERISTICS
(Notes 6, 8, 9) (0
°
C
≤
T
A
≤
+70
°
C; V
DD
, V
DD
Q = +3.3V ±0.165V)
-10
-12
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Clock enable (CKE#)
Control signals
Data-in
Hold Times
Address
Clock enable (CKE#)
Control signals
Data-in
SYMBOL
MIN
MAX
MIN
MAX UNITS
NOTES
t
KHKH
f
KF
t
KHKL
t
KLKH
10
12
ns
100
83
MHz
ns
ns
3.0
3.0
4.0
4.0
1
1
t
KHQV
t
KHQX
t
KHQX1
t
KHQZ
t
GLQV
t
GLQX
t
GHQZ
7.5
9.0
ns
ns
ns
ns
ns
ns
ns
3.0
3.0
3.0
3.0
2
2, 3, 4, 5
2, 3, 4, 5
6
2, 3, 4, 5
2, 3, 4, 5
5.0
5.0
5.0
5.0
0
0
5.0
5.0
t
AVKH
t
EVKH
t
CVKH
t
DVKH
2.0
2.0
2.0
2.0
2.5
2.5
2.5
2.5
ns
ns
ns
ns
7
7
7
7
t
KHAX
t
KHEX
t
KHCX
t
KHDX
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
7
7
7
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT55L64L36F1 | 64K x 36,3.3V I/O, ZBT SRAM(2Mb,3.3V輸入/輸出，靜態(tài)RAM) |
| MT55L64L36P1 | 64K x 36, 3.3V I/O, ZBT SRAM( 2Mb,3.3V輸入/輸出，靜態(tài)RAM) |
| MT58L128L18FT-10 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128L18FT-6.8 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128L18FT-7.5 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L64L32F1T-10 | 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V |
| MT55L64L32F1T-12 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 2M-Bit 64K x 32 9ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L64L32F1T-12IT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L64L32P1T10 | 制造商:MT 功能描述:New |
| MT55L64L36F1T-12 | 制造商:Cypress Semiconductor 功能描述:64KX36 SRAM PLASTIC TQFP 3.3V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。