參數(shù)資料
型號(hào)： MT55L64L32F1
廠商： Micron Technology, Inc.
英文描述： 64K x 32,3.3V I/O, ZBT SRAM(2Mb,3.3V輸入/輸出，靜態(tài)RAM)
中文描述： 64K的x 32,3.3六/ O的ZBT SRAM的（處理器，3.3V的輸入/輸出，靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 3/23頁(yè)
文件大?。?/td> 406K
代理商： MT55L64L32F1
3
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM
MT55L128L18F1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, FLOW-THROUGH ZBT SRAM
GENERAL DESCRIPTION (continued)
for easy depth expansion (CE2, CE2#), cycle start input
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc# and BWd#) and
read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal
minimization), clock (CLK) and snooze enable (ZZ,
which may be tied LOW if unused). There is also a burst
mode pin (MODE) that selects between interleaved and
linear burst modes. MODE may be tied HIGH, LOW or
left unconnected if burst is unused. The flow-through
data-out (Q) is enabled by OE#. WRITE cycles can be
from one to four bytes wide as controlled by the write
control inputs.
All READ, WRITE and DESELECT cycles are initiated
by the ADV/LD# input. Subsequent burst addresses can
be internally generated as controlled by the burst
advance pin (ADV/LD#). Use of burst mode is optional.
It is allowable to give an address for each individual
READ and WRITE cycle. BURST cycles wrap around
after the fourth access from a base address.
PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x18
NC
NC
NC
x32
NC
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
SS
V
DD
V
DD
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
x36
DQPc
DQc
DQc
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
DQb
DQb
DQc
DQc
DQb
DQb
DQd
DQd
DQb
DQb
DQPb
NC
DQd
DQd
DQd
DQd
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32
V
SS
V
DD
Q
DQd
D
Qd
NC
x36
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
NC
NC
NC
NC
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
ZZ
V
DD
V
SS
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
DQPa
DQa
DQa
NC
NC
DQa
DQa
DQa
DQa
DQb
DQb
DQa
DQa
DQPa
NC
DQb
DQb
DQb
DQb
PIN #
x18
x32
x36
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
V
SS
V
DD
Q
DQb
DQb
NC
SA
SA
NF*
NF*
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc# BWc#
BWd# BWd#
CE2
CE#
SA
SA
NC
NC
SA
DQb
DQb
DQPb
NC
NC
NC
NC
NC
DQd
DQd
DQPd
MODE (LBO#)
SA
SA
SA
SA
SA1
SA0
DNU
DNU
V
SS
V
DD
DNU
DNU
SA
SA
SA
SA
SA
SA
NC/
SA
*
PIN #
x18
x32
x36
* Pins 50, 83, and 84 are reserved for address expansion.
To allow for continuous, 100 percent use of the data
bus, the flow-through ZBT SRAM uses a LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The write data associated with the address
is required one cycle later, or on the rising edge of clock
cycle two.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa#
controls DQa pins; BWb# controls DQb pins; BWc#
controls DQc pins; and BWd# controls DQd pins. Cycle
types can only be defined when an address is loaded,
i.e., when ADV/LD# is LOW. Parity/ECC bits are only
available on the x18 and x36 versions.
Micron’s 2Mb ZBT
SRAMs operate from a +3.3V V
DD
power supply, and all inputs and outputs are LVTTL-
compatible. The device is ideally suited for systems
requiring high bandwidth and zero bus turnaround
delays.
refer (
www.micronsemi.com/datasheets/zbtds.html
) for the
Micron’s site
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