參數(shù)資料
型號(hào)： MT55L64L32F1
廠商： Micron Technology, Inc.
英文描述： 64K x 32,3.3V I/O, ZBT SRAM(2Mb,3.3V輸入/輸出，靜態(tài)RAM)
中文描述： 64K的x 32,3.3六/ O的ZBT SRAM的（處理器，3.3V的輸入/輸出，靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 6/23頁(yè)
文件大小： 406K
代理商： MT55L64L32F1
6
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM
MT55L128L18F1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, FLOW-THROUGH ZBT SRAM
PIN DESCRIPTIONS (continued)
TQFP (x18)
88
TQFP (x32/x36)
88
SYMBOL
R/W#
TYPE
Input
DESCRIPTION
Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted
into WRITEs (and vice versa) other than by loading a new
address. A LOW on this pin permits BYTE WRITE opera-
tions and must meet the setup and hold times around the
rising edge of CLK. Full bus-width WRITEs occur if all byte
write enables are LOW.
Mode: This input selects the burst sequence. A LOW on
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
SRAM Data I/Os: Byte
“
a
”
is DQa pins; Byte
“
b
”
is DQb
pins; Byte
“
c
”
is DQc pins; Byte
“
d
”
is DQd pins. Input data
must meet setup and hold times around the rising edge of
CLK.
31
31
MODE
(LBO#)
Input
(a)
58, 59, 62, 63,
68, 69, 72-74
(b)
8, 9, 12, 13,
18, 19, 22-24
(a)
52, 53,
56-59, 62, 63
(b)
68, 69,
72-75, 78, 79
(c)
2, 3, 6-9,
12, 13
(d)
18, 19,
22-25, 28, 29
51
80
1
30
n/a
DQa
Input/
Output
DQb
DQc
DQd
74
24
NC/
DQPa
NC/
DQPb
NC/
DQPc
NC/
DQPd
NC
NC/
I/O
No Connect/Data Bits: On the x32 version, these pins are
no connect (NC) and can be left floating or connected to
GND to minimize thermal impedance. On the x36 version,
these bits are DQs.
No Connect: These pins can be left floating or connected
to GND to minimize thermal impedance.
1-3, 6, 7, 25,
28-30, 51-53,
56, 57, 75, 78,
79, 95, 96
50
NC
50
NC/SA
NC
No Connect: NC pin 50 is reserved as an address bit for the
higher-density 4Mb ZBT SRAM. This pin can be left
floating or connected to GND to minimize thermal
impedance.
Power Supply:
See DC Electrical Characteristics and
Operating Conditions for range.
Isolated Output Buffer Supply:
See DC Electrical
Characteristics and Operating Conditions for range.
Ground:
GND.
15, 16, 41, 65, 91 15, 16, 41, 65, 91
V
DD
Supply
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 14, 17,
21, 26, 40, 55,
60, 66, 67, 71,
76, 90
38, 39, 42, 43
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 14, 17,
21, 26, 40, 55,
60, 66, 67, 71,
76, 90
38, 39, 42, 43
V
DD
Q
Supply
V
SS
Supply
DNU
–
Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
No Function: These pins are internally connected to the
die and will have the capacitance of an input pin. It is
allowable to leave these pins unconnected or driven by
signals. Pins 83 and 84 are reserved as address bits for the
8Mb and 16Mb ZBT SRAMs.
83, 84
83, 84
NF
–
相關(guān)PDF資料
PDF描述
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