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參數(shù)資料
| 型號： | MT54V512H18E |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲器) |
| 中文描述： | 為512k × 18同步流水線突發(fā)靜態(tài)存儲器（9Mb以上，流水線式，同步脈沖靜態(tài)存儲器） |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 260K |
| 代理商： | MT54V512H18E |
9
512K x 18 2.5V V
DD
, HSTL, QDRb4 SRAM
MT54V512H18E.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb4 SRAM
NOTE:
1. X means “ Don’t Care.” H means logic HIGH. L means logic LOW.
-
means rising edge;
ˉ
means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges except if C
and C# are HIGH then data outputs are delivered at K and K# rising edges.
3. R# and W# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at the rising
edge of K.
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = /K# = C = /C# when clock is stopped. This is not essential but permits most rapid restart by
overcoming transmission line charging symmetrically.
7. If this signal was LOW to initiate the previous cycle, this signal becomes a don't care for this operation however it is
strongly recommended that this signal is brought HIGH as shown in the truth table.
8. This signal was HIGH on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecutive
K clock rising edges is not permitted. The device will ignore the second request.
9. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
BY TE WRITE OPERATION
9
OPERATION
K
K#
BW0#
BW1#
WRITE D0-17 at K rising edge
WRITE D0-17 at K# rising edge
WRITE D0-8 at K rising edge
WRITE D0-8 at K# rising edge
WRITE D9-17 at K rising edge
WRITE D9-17 at K# rising edge
WRITE nothing at K rising edge
WRITE nothing at K# rising edge
L
H
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
L
H
L
H
L
H
L
H
L
H
L
H
L
H
TRUTH TABLE
(Notes 1-8)
OPERATION
K
R#
W#
D OR Q
D OR Q
D OR Q
D OR Q
WRITE Cycle:
Load address,input write data on 2
consecutive K and K# rising edges
READ Cycle:
Load address, output data on 2
consecutive C AND C# rising edges
NOP: No operation
L
H
H
7
L
8
D
A
(A+0)
at
K(t+1)
-
Q
A
(A+0)
at
C(t+1)
-
D = X
Q = High-Z
Previous
State
D
A
(A+1)
at
K#(t+1)
-
Q
A
(A+1)
at
C#(t+1)
-
D = X
Q = High-Z Q = High-Z
Previous
State
D
A
(A+2)
at
K(t+2)
-
Q
A
(A+2)
at
C(t+2)
-
D = X
D
A
(A+3)
at
K#(t+2)
-
Q
A
(A+3)
at
C#(t+2)
-
D = X
Q = High-Z
Previous
State
L
H
L
8
X
L
H
H
H
STANDBY: Clock stopped
Stopped
X
X
Previous
State
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT54V512H18E1F-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-6 | 制造商:Cypress Semiconductor 功能描述:DS2KX18 SRAM PLASTIC FBGA 2.5V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT54V512H18EF-6C | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT54V512H36EF-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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