參數(shù)資料
型號: MT54V512H18E
廠商: Micron Technology, Inc.
英文描述: 512K x 18 Synchronous Pipelined Burst SRAM(9Mb,流水線式,同步脈沖靜態(tài)存儲器)
中文描述: 為512k × 18同步流水線突發(fā)靜態(tài)存儲器(9Mb以上,流水線式,同步脈沖靜態(tài)存儲器)
文件頁數(shù): 17/22頁
文件大?。?/td> 260K
代理商: MT54V512H18E
17
512K x 18 2.5V V
DD
, HSTL, QDRb4 SRAM
MT54V512H18E.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb4 SRAM
EXTEST
EX TEST is a mandatory 1149.1 instruction which is
to be executed whenever the instruction register is
loaded with all 0s. EX TEST is not implemented in the
TAP controller, hence this device is not IEEE 1149.1
compliant.
The TAP controller does recognize an all-0 instruc-
tion. When an EX TEST instruction is loaded into the
instruction register, the SRAM responds as if a SAMPLE/
PRELOAD instruction has been loaded. EX TEST does
not place the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific,
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI and
TDO pins and allows the IDCODE to be shifted out of
the device when the TAP controller enters the Shift-DR
state. The IDCODE instruction is loaded into the in-
struction register upon power-up or whenever the TAP
controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded
into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bi-directional pins is captured in the boundary
scan register.
The user must be aware that the TAP controller clock
can only operate at a frequency up to 10 MHz, while the
SRAM clock operates more than an order of magnitude
faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR
state, an input or output will undergo a transition. The
TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but
there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will
capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP
controller’s capture setup plus hold time (
t
CS plus
t
CH).
The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in
the boundary scan register.
Once the data is captured, it is possible to shift out the
data by putting the TAP into the Shift-DR state. This
places the boundary scan register between the TDI and
TDO pins.
Note that since the PRELOAD part of the command
is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
BY PASS
When the BYPASS instruction is loaded in the in-
struction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between TDI and
TDO. The advantage of the BYPASS instruction is that
it shortens the boundary scan path when multiple
devices are connected together on a board.
RESERVED
These instruction are not implemented but are re-
served for future use. Do not use these instructions.
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