參數(shù)資料
型號(hào)： MT54V512H18E
廠商： Micron Technology, Inc.
英文描述： 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲(chǔ)器)
中文描述： 為512k × 18同步流水線突發(fā)靜態(tài)存儲(chǔ)器（9Mb以上，流水線式，同步脈沖靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 16/22頁(yè)
文件大?。?/td> 260K
代理商： MT54V512H18E
16
512K x 18 2.5V V
DD
, HSTL, QDRb4 SRAM
MT54V512H18E.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb4 SRAM
TEST DATA-OUT (TDO)
The TDO output pin is used to serially clock data-out
from the registers. The output is active depending upon
the current state of the TAP state machine. (See Figure
2.) The output changes on the falling edge of TCK. TDO
is connected to the least significant bit (LSB) of any
register. (See Figure 3.)
PERFORMING A TAP RESET
A RESET is performed by forcing TMS HIGH (V
DD
) for
five rising edges of TCK. This RESET does not affect the
operation of the SRAM and may be performed while the
SRAM is operating.
At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO
pins and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected at
a time through the instruction register. Data is serially
loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
INSTRUCTION REGISTER
Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in
Figure 2. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state,
the two least significant bits are loaded with a binary
“01” pattern to allow for fault isolation of the board-
level serial test data path.
BY PASS REGISTER
To save time when serially shifting data through
registers, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that can
be placed between the TDI and TDO pins. This allows
data to be shifted through the SRAM with minimal
delay. The bypass register is set LOW (V
SS
) when the
BYPASS instruction is executed.
BOUNDARY SCAN REGISTER
The boundary scan register is connected to all the
input and bidirectional pins on the SRAM. Several no
connect (NC) pins are also included in the scan register
to reserve pins. The x18 configuration has a 69-bit-long
register.
The boundary scan register is loaded with the con-
tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO pins when the controller is moved to the
Shift-DR state. The EX TEST, SAMPLE/PRELOAD, and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.
The Boundary Scan Order table shows the order in
which the bits are connected. Each bit corresponds to
one of the pins on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected
to TDO.
IDENTIFICATION (ID) REGISTER
The ID register is loaded with a vendor-specific, 32-
bit code during the Capture-DR state when the IDCODE
command is loaded in the instruction register. The
IDCODE is hardwired into the SRAM and can be shifted
out when the TAP controller is in the Shift-DR state.
The ID register has a vendor code and other informa-
tion described in the Identification Register Definitions
table.
TAP INSTRUCTION SET
OVERVIEW
Eight different instructions are possible with the
three-bit instruction register. All combinations are listed
in the Instruction Codes table. Three of these instruc-
tions are listed as RESERVED and should not be used.
The other five instructions are described in detail be-
low.
The TAP controller used in this SRAM is not fully
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EX TEST or INTEST or
the PRELOAD portion of SAMPLE/PRELOAD; rather it
performs a capture of the I/O ring when these instruc-
tions are executed.
Instructions are loaded into the TAP controller dur-
ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state, in-
structions are shifted through the instruction register
through the TDI and TDO pins. To execute the instruc-
tion once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
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