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參數(shù)資料
| 型號： | MT54V512H18E |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲(chǔ)器) |
| 中文描述： | 為512k × 18同步流水線突發(fā)靜態(tài)存儲(chǔ)器（9Mb以上，流水線式，同步脈沖靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 11/22頁 |
| 文件大?。?/td> | 260K |
| 代理商： | MT54V512H18E |
11
512K x 18 2.5V V
DD
, HSTL, QDRb4 SRAM
MT54V512H18E.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb4 SRAM
MAX
-7.5
NOTE:
1. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times and
greater output loading. Typical value is measured at 6ns cycle time.
2. Typical values are measured at V
DD
= 2.5V, V
DD
Q = 1.5V and temperature = 25°C.
3. Operating supply currents and burst mode currents are calculated with 50 percent READ cycles and 50 percent WRITE
cycles.
4. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.
5. Average I/O current and power is provided for information purposes only and is not tested. Calculation assumes that
all outputs are loaded with C
L
(in farads) f = input clock frequency, half of outputs toggle at each transition (n=18),
V
DD
Q=1.5V and uses the equations: Average I/O Power as dissipated by the SRAM is:
P = 0.5 * n * f * C
L
* V
DD
Q
2
. Average I
DD
Q = n * f * C
L
* V
DD
Q.
6. This parameter is sampled.
7. Average thermal resistance between the die and the case top surface per MIL SPEC 883 Method 1012.1.
8. Junction temperature is a function of total device power dissipation and device mounting environment. Measured per
SEMI G38-87.
THERMAL RESISTANCE
DESCRIPTION
Junction to Ambient (Airflow of 1m/s) Soldered on a 4.25 x 1.125 inch,
Junction to Case (Top)
Junction to Pins (Bottom)
CONDITIONS
SYMBOL
q
JA
q
JC
q
JB
TYP
25
10
12
UNITS
°C/W
°C/W
°C/W
NOTES
6, 7
6
6, 8
4-layer printed circuit board
CAPACITANCE
DESCRIPTION
Address/Control Input Capacitance
Input, Output Capacitance (D, Q)
Clock Capacitance
CONDITIONS
SYMBOL
C
I
C
O
C
CK
TYP
4
6
5
MAX
5
7
6
UNITS
pF
pF
pF
NOTES
6
6
6
T
A
= 25°C; f = 1 MHz
I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS
(+20°C
￡
T
J
￡
+110°C; V
DD
= MAX unless otherwise noted)
DESCRIPTION
Operating Supply
Current: DDR
CONDITIONS
All inputs
￡
V
IL
or
3
V
IH
;
Cycle time
3
t
KHKH (MIN);
Outputs open
t
KHKH =
t
KHKH (MIN);
Device in NOP state;
All addresses/data static
C
L
= 15pF
SYMBOL
TYP
-6
-10
UNITS NOTES
I
DD
TBD
350
280
220
mA
1, 2,
3
2, 4
Standby Supply
Current: NOP
I
SB
1
TBD
170
140
110
mA
Output Supply
Current: DDR
(For information only)
I
DD
Q
34
27
20
mA
5
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT54V512H18E1F-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT54V512H18EF-6 | 制造商:Cypress Semiconductor 功能描述:DS2KX18 SRAM PLASTIC FBGA 2.5V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT54V512H18EF-6C | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT54V512H36EF-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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