參數(shù)資料
型號: MT54V512H18E
廠商: Micron Technology, Inc.
英文描述: 512K x 18 Synchronous Pipelined Burst SRAM(9Mb,流水線式,同步脈沖靜態(tài)存儲器)
中文描述: 為512k × 18同步流水線突發(fā)靜態(tài)存儲器(9Mb以上,流水線式,同步脈沖靜態(tài)存儲器)
文件頁數(shù): 20/22頁
文件大?。?/td> 260K
代理商: MT54V512H18E
20
512K x 18 2.5V V
DD
, HSTL, QDRb4 SRAM
MT54V512H18E.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb4 SRAM
IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD
REVISION NUMBER
(31:29)
DEVICE ID
(28:12)
MICRON JEDEC ID
CODE (11:1)
ID Register Presence
Indicator (0)
512K x 18
000
DESCRIPTION
Version number.
00011000011000000
512K x18 QDR 4-word burst.
00000101100
Allows unique identification of SRAM vendor.
1
Indicates the presence of an ID register.
SCAN REGISTER SIZES
REGISTER NAME
Instruction
Bypass
ID
Boundary Scan
BIT SIZE (x18)
3
1
32
69
INSTRUCTION CODES
INSTRUCTION
EXTEST
CODE
000
DESCRIPTION
Captures I/O ring contents. Places the boundary scan register between TDI and
TDO. This operation does not affect SRAM operations. This instruction is not
1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and
TDO. Does not affect SRAM operation. This instruction does not implement
1149.1 preload function and is therefore not 1149.1-compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operations.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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