- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385639 > MT46V2M32LG (Micron Technology, Inc.) DOUBLE DATA RATE DDR SDRAM PDF資料下載
參數(shù)資料
| 型號： | MT46V2M32LG |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 5/65頁 |
| 文件大?。?/td> | 2360K |
| 代理商： | MT46V2M32LG |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁
5
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
PIN DESCRIPTIONS
TQFP PIN NUMBERS
55, 54
SYMBOL
CK, CK#
TYPE
Input
DESCRIPTION
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE
in any bank). CKE is synchronous for POWER-DOWN entry and
exit, and for SELF REFRESH entry. CKE is asynchronous for SELF
REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after V
DD
is applied.
Chip Select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A8) for READ/
WRITE commands, to select one location out of the memory array
in the respective bank. A8 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
bank (A8 LOW, bank selected by BA0, BA1) or all banks (A8
HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data Input/Output:
53
CKE
Input
28
CS#
Input
27, 26, 25
RAS#, CAS#, Input
WE#
DM0-DM3 Input
23, 56, 24, 57
29, 30
BA0, BA1
Input
31-34, 47-51, 45, 36
A0-A10
Input
97, 98, 100, 1, 3, 4, 6, 7
60, 61, 63, 64, 68, 69, 71, 72
9, 10, 12, 13, 17, 18, 20, 21
74, 75, 77, 78, 80, 81, 83, 84
DQ0-31
I/O
(continued on next page)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT46V2M32V1 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4-1 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75 | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75L | DOUBLE DATA RATE DDR SDRAM |
| MT46V32M4TG-75Z | DOUBLE DATA RATE DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V2M32V1 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16 | 制造商:Micron Technology Inc 功能描述:32MX16 DDR SDRAM PLASTIC IND TEMP BGA 2.6V DDR - Trays |
| MT46V32M16-5B | 制造商:Micron Technology Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。