參數(shù)資料
型號(hào)： MT46V2M32LG
廠商： Micron Technology, Inc.
英文描述： DOUBLE DATA RATE DDR SDRAM
中文描述： 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁數(shù)： 46/65頁
文件大小： 2360K
代理商： MT46V2M32LG
46
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1-5, 14-17, 33; notes appear on pages 47
–
50 ) (0
°
C
≤
T
A
≤
+70
°
C; V
DD
Q = +2.65V, V
DD
= +2.65V)
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
CL = 3
CL = 2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time
Address and control input setup time
Address and control input pulse width
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
-6
-65
SYMBOL
t
AC
t
CH
t
CL
t
CK (3)
t
CK (2)
t
DH
t
DS
t
DIPW
t
DQSCK
t
DQSH
t
DQSL
t
DQSQ
t
DQSS
t
DSS
t
DSH
t
HP
t
HZ
t
LZ
t
IH
t
IS
t
IPW
t
MRD
t
QH
MIN
-0.75
0.45
0.45
6
10
0.6
0.6
1.5
-0.75
0.4
0.4
MAX
+0.75
0.55
0.55
12
12
MIN
-0.75
0.45
0.45
6.5
10
0.6
0.6
1.5
-0.75
0.4
0.4
MAX
+0.75
0.55
0.55
12
12
UNITS
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
t
CK
ns
NOTES
30
30
41
26, 31
26, 31
31
+0.75
+0.75
0.5
1.25
0.5
1.25
25, 26
0.75
0.25
0.2
t
CH,
t
CL
-0.6
-0.6
1
1
2
2
t
HP
-0.65ns
40
t
RAS(MIN) - (burst length *
t
CK/2)
58
66
0.75
0.25
0.2
t
CH,
t
CL
-0.65
-0.65
1
1
2
2
t
HP
-0.7ns
40
34
18
18
14
14
25, 26
34
35
45
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
REFRESH to REFRESH command interval
Average periodic refresh interval
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS Read preamble
DQS Read postamble
ACTIVE bank
a
to ACTIVE bank
b
command
Terminating voltage delay to V
DD
DQS Write preamble
DQS Write preamble setup time
DQS Write postamble
Write recovery time
Internal WRITE to READ command delay
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Data valid output window
t
RAS
t
RAP
t
RC
t
RFC
t
REFC
t
REFI
t
RCD
t
RP
t
RPRE
t
RPST
t
RRD
t
VTD
t
WPRE
t
WPRES
t
WPST
t
WR
t
WTR
t
XSNR
t
XSRD
na
120K
120K
ns
ns
ns
ns
μs
μs
ns
ns
t
CK
t
CK
t
CK
ns
t
CK
ns
t
CK
t
CK
t
CK
ns
t
CK
ns
59.5
66
40
23
23
7.8
7.8
18
18
0.9
0.4
2
0
0.25
0
0.4
2
1
66
200
19.5
19.5
0.9
0.4
2
0
0.25
0
0.4
2
1
66
200
1.1
0.6
1.1
0.6
0
0
20, 21
19
0.6
0.6
t
QH-
t
DQSQ
t
QH-
t
DQSQ
25
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