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參數(shù)資料
| 型號： | MT46V2M32LG |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 44/65頁 |
| 文件大?。?/td> | 2360K |
| 代理商： | MT46V2M32LG |
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44
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
I
DD
SPECIFICATIONS AND CONDITIONS
(Notes: 1-5, 10, 12, 14; notes appear on pages 47
–
50) (0
°
C
≤
T
A
≤
+70
°
C; V
DD
Q = 2.5V/+2.65V, V
DD
=2.5V/+2.65V)
PARAMETER/CONDITION
Operating Current: One bank; Active-Precharge;
t
RC =
t
RC MIN;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice
per clock cyle; Address and control inputs changing once
per clock cycle
Operating Current: One bank; Active-Read-Precharge;
Burst = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); I
OUT
= 0mA;
Address and control inputs changing once per clock cycle
Precharge Power-Down Standby Current: All banks idle;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
Idle Standby Current: CS# = HIGH; All banks idle;
t
CK =
t
CK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle
Active Power-Down Standby Current: One bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
Active Standby Current: CS# = HIGH; CKE = HIGH;
One bank; Active-Precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
Operating Current: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN); I
OUT
= 0mA
Operating Current: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
Auto Refresh Current
SYMBOL
I
DD
0
-5
-55
175
-6
-65
155
UNITS NOTES
mA
180
165
22
I
DD
1
200
195
190
185
mA
22
I
DD
2P
3
3
3
3
mA
32
I
DD
2N
120
110
100
90
mA
I
DD
3P
70
65
60
55
mA
32
I
DD
3N
125
113
105
95
mA
22
I
DD
4R
355
330
310
295
mA
I
DD
4W
270
250
240
220
mA
t
RC =
t
RFC (MIN)
t
RC =
7.8μs
Standard
I
DD
5
I
DD
6
I
DD
7
245
3.5
2
245
3.5
2
245
3.5
2
245
3.5
2
mA
mA
mA
22
27
11
Self Refresh Current: CKE
≤
0.2V
MAX
CAPACITANCE
(Note: 13; notes appear on pages 47
–
50)
PARAMETER
Delta Input/Output Capacitance: DQs, DQS, DM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL
DC
IO
DC
I
1
DC
I
2
C
IO
C
I
1
C
I
2
C
I
3
MIN
–
–
–
4.0
2.0
2.0
2.0
MAX
0.50
0.50
0.25
5.0
3.0
3.5
3.5
UNITS
pF
pF
pF
pF
pF
pF
pF
NOTES
29
29
29
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