
1
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
KEY TIMING PARAMETERS
SPEED
GRADE
-5
-55
-6
-65
CLOCK RATE
CL = 2**
125 MHz
100 MHz
100 MHz
100 MHz
DATA-OUT
WINDOW* WINDOW
1.5ns
1.8ns
1.9ns
2.1ns
ACCESS
DQS-DQ
SKEW
+0.5ns
+0.5ns
+0.5ns
+0.5ns
CL = 3**
200 MHz
183 MHz
166 MHz
150 MHz
±0.75ns
±0.75ns
±0.75ns
±0.75ns
*Minimum clock rate @ CL = 3
**CL = CAS (Read) Latency
DOUBLE DATA RATE
(DDR) SDRAM
MT46V2M32V1- 512K x 32 x 4 banks
MT46V2M32 - 512K x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron
www.micron.com/dramdsPIN ASSIGNMENT (TOP VIEW)
100-Pin TQFP
(Normal Bend Shown)
FEATURES
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Reduced output drive option
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) for masking write data
Programmable burst lengths: 2, 4, 8, or full page
32ms, 4,096-cycle auto refresh (7.8μs/cycle)
Auto precharge option
Auto Refresh and Self Refresh Modes
Programmable I/O (SSTL_2 compatible) – reduced
and impedance matched
OPTIONS
Configuration
2 Meg x 32
Power Supply
2.5V V
DD
/V
DD
Q
2.65V V
DD
/V
DD
Q
Plastic Package
100-pin TQFP (0.65mm lead pitch)
Timing - Cycle Time
200 MHz @ CL = 3
183 MHz @ CL = 3
166 MHz @ CL = 3
150 MHz @ CL = 3
MARKING
(512K x 32 x 4 banks)
2M32
V1
none
LG
-5
-55
-6
-65
D
V
S
Q
D
D
V
D
V
D
Q
D
N
V
S
Q
D
N
N
N
N
V
D
Q
V
S
D
D
V
S
Q
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
313233343536
38 3940414243
37
45 4647484950
44
100999897969594939291 90 89888786 8584838281
DQ28
V
DD
Q
DQ27
DQ26
V
SS
Q
DQ25
DQ24
V
DD
Q
DQ15
DQ14
V
SS
Q
DQ13
DQ12
V
DD
Q
V
SS
V
DD
DQ11
DQ10
V
SS
Q
DQ9
DQ8
V
DD
Q
V
REF
DM3
DM1
CK
CK#
CKE
NC/MCL
A8/AP
A
A
A
A
V
D
A
N
N
N
N
N
N
N
N
A
V
S
A
A
A
A
DQ3
V
DD
Q
DQ4
DQ5
V
SS
Q
DQ6
DQ7
V
DD
Q
DQ16
DQ17
V
SS
Q
DQ18
DQ19
V
DD
Q
V
DD
V
SS
DQ20
DQ21
V
SS
Q
DQ22
DQ23
V
DD
Q
DM0
DM2
WE#
CAS#
RAS#
CS#
BA0
BA1
64Mb (x32) DDR SDRAM PART NUMBER
PART NUMBER
MT46V2M32LG
ARCHITECTURE
2 Meg x 32
Part Number Example:
MT46V2M32V1LG-5
2 Meg x 32
512K x 32 x 4 banks
4K
2K (A0-A10)
4 (BA0, BA1)
256 (A0-A7)
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing